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Compact and low power ADCs for a MEMS-based probe storage device

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Abstract

In this paper, we investigate the most appropriate ADC for an array of probe storage devices. Power consumption and area are crucial in this application, since one ADC is associated with each read channel. The read-channel specifications of the probe storage device require an ADC with seven bits of resolution at a rate of 100 kSample/s. Five different ADC architectures have been implemented for the desired specifications: a first- and a second order discrete-time \(\Sigma\Delta,\) a second order continuous-time \(\Sigma\Delta\) and a cyclic ADC. The system and circuit design methods of each architecture are presented. The different architectures are compared based on the measurement results of the five fabricated circuits.

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References

  1. Trinh, C., et al. (2009, February). A 5.6 MB/s 64 Gb 4 b/cell NAND flash memory in 43 nm CMOS. In IEEE International Solid State Circuits Conference, ISSCC’09.

  2. Vettiger, P., Cross, G., Despont, M., Drechsler, U., Duerig, U., Gotsmann, B., Hberle, W., Lantz, M. A., Rothuizen, H. E., Stutz, R., & Binnig, G. K. (2002). The “millipede”—nanotechnology entering data storage. IEEE Transactions on Nanotechnology, 1, 39–55.

    Article  Google Scholar 

  3. Eleftheriou, E., Antonakopoulos, T., Binnig, G. K., Cherubini, G., Despont, M., Dholakia, A., Duerig, U., Lantz, M. A., Pozidis, H., Rothuizen H. E., & Vettiger, P. (2003). Millipede—a MEMS-based scanning-probe data-storage system. IEEE Transactions on Magnetics, 39(2), 938–945.

    Article  Google Scholar 

  4. Wiesmann, D., Duerig, U., Gotsmann, B., Knoll, A., Pozidis, H., Porro, F., & Vecchione, R. (2007, June). Ultra-high storage densities with thermo-mechanical probes and polymer media. In Innovative Mass Storage Technologies Conference, Enschede, The Netherlands.

  5. Loeliger, T., Bachtold, P., Binnig, G., Cherubini, G., Durig, U., Eleftheriou, E., & Vettiger, P. (2002, September). CMOS sensor array with cell level analog-to-digital conversion for local probe data storage. IEEE European Solid-State Circuits Conference, Florence, Italy.

  6. Hagleitner, C., Bonaccio, T., Rothuizen, H., Lienemann, J., Wiesmann, D., Cherubini, G., Korvink, J. G., & Eleftheriou, E. (2007). Modeling, design, and verification for the analog front-end of a MEMS-based parallel scanning-probe storage device. IEEE Journal of Solid-State Circuits, 42(8), 1779–1789.

    Article  Google Scholar 

  7. Yang, D., Fowler, B., & El Gamal, A. (1998, September). A Nyquist rate pixel level ADC for CMOS image sensors. In IEEE Custom Integrated Circuits Conference, CICC’98, Santa Clara, CA, USA.

  8. Hagleitner, C., Bonaccio, T., Pantazi, A., Sebastian, A., & Eleftheriou, E. (2006, June). An analog frontend chip for a MEMS-based parallel scanning-probe data-storage system. In IEEE Symposium on VLSI Circuits.

  9. Fowler, B., El Gamal, A., & Yang, D. (1998). Techniques for pixel level analog to digital conversion. In SPIE Conference on Infrared Readout Electronics IV, SPIE Vol. 3360, Orlando, FL.

  10. Scott, M. D., Boser, B. E., & Pister, K. S. J. (2003). An ultralow-energy ADC for smart dust. IEEE Journal of Solid-State Circuits, 38(7), 1123–1129.

    Article  Google Scholar 

  11. Borghetti, F., Nielsen, J. H., Ferragina, V., Malcovati, P., Andreani, P., & Baschirotto, A. (2006, September). A programmable 10 b up-to-6 MS/s SAR-ADC featuring constant-FoM with on-chip reference voltage buffers. In IEEE European Solid State Circuits Conference.

  12. Castello, R., & Gray, P. R. (1985). A high-performance micropower switched-capacitor filter. IEEE Journal of Solid-State Circuits, 20(6), 1122–1132.

    Article  Google Scholar 

  13. Choksi, O., & Carley, R. (2003). Analysis of switched-capacitor common-mode feedback circuit. IEEE Transactions on Circuits and Systems, Part II, 50(12), 906–917.

    Article  Google Scholar 

  14. Razavi, B. (1995). Principles of data conversion systems. Piscataway, NJ: IEEE Press.

    Google Scholar 

  15. Furuta, M., Kawahito, S., Inoue, T., & Nishikawa, Y. (2005, September). A cyclic A/D converter with pixel noise and column wise offset canceling for CMOS image sensors. In IEEE European Solid-State Circuits Conference, Grenoble, France.

  16. Aboushady, H., & Louerat, M. M. (2002, May). Systematic approach for discrete-time to continuous-time transformation of Sigma–Delta modulators. In IEEE International Symposium on Circuits and Systems, Phoenix, AZ, USA.

  17. Beilleau, N., Aboushady, H., & Louerat, M. M. (2003, December). Systematic approach for scaling coefficients of discrete-time and continuous-time Sigma–Delta modulators. In IEEE Midwest Symposium on Symposium on Circuits and Systems, Cairo, Egypt.

  18. Aboushady, H., Montaudon, F., Paillardet, F., & Louerat, M. M. (2002, September). A 5 mW, 100 kHz bandwidth, current-mode continuous-time Sigma–Delta modulator with 84 dB dynamic range. In IEEE European Solid-State Circuits Conference, Florence, Italy.

  19. Smith, S., & Sanchez-Sinencio, E. (1996). Low-voltage integrators for high-frequency CMOS filters using current mode techniques. IEEE Transactions on Circuits and Systems, Part II, 43(1), 39–48.

    Article  Google Scholar 

  20. Zele, R., & Allstot, D. (1996). Low-power CMOS continuous-time filters. IEEE Journal of Solid-State Circuits, 31(2), 157–168.

    Article  Google Scholar 

  21. Aboushady, H., & Louerat, M. M. (2001, May). Low-power design of low-voltage current-mode integrators for continuous-time Sigma–Delta modulators. In IEEE International Symposium on Circuits and Systems, Sydney, Australia.

  22. Medeiro, F., Verdu, A. P., & Rodriguez-Vazquez, A. (1999). Top-down-design of high performances Sigma–Delta modulators. Boston: Kluwer Academic Publishers.

    Book  Google Scholar 

  23. Roeintan, L. G., & Sodagar, A. M. (1994). High speed current-mode sense amplifier. Electronics Letters, 30(17), 1371–1372.

    Article  Google Scholar 

  24. Maurino, R., & Mole, P. (2000). A 200 MHz IF 11-bit fourth order bandpass Delta–Sigma ADC in SiGe. IEEE Journal of Solid-State Circuits, 35(7), 959–967.

    Article  Google Scholar 

  25. Kim, J., & Murmann, B. (2012). A 12-b, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration. IEEE Journal of Solid-State Circuits, 47(9), 2141–2151.

    Article  Google Scholar 

  26. Gambini, S., & Rabaey, J. (2007, September). A 100 KS/s 65 dB DR Sigma–Delta ADC with 0.65 V supply voltage. In IEEE European Solid-State Circuits Conference, Munich, Germany.

  27. Verma, N., & Chandrakasan, A. (2007). An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes. IEEE Journal of Solid-State Circuits, 42(6), 1196–1205.

    Article  Google Scholar 

  28. Jarvinen, J., Saukoski, M., & Halonen, K. (2008). A 12-bit ratio-independent algorithmic A/D converter for a capacitive sensor interface. IEEE Transactions on Circuits and Systems, Part I, 55(3), 730–740.

    Article  MathSciNet  Google Scholar 

  29. Guo, J., Yuan, J. J., Huang, J., Law, J., Yeung, C., & Chan, M. (2012). 32.9 nV/rt Hz—60.6 dB THD dual-band micro-electrode array signal acquisition IC. IEEE Journal of Solid-State Circuits, 47(5), 1209–1220.

    Article  Google Scholar 

  30. Samid, L., & Manoli, Y. (2006, September). A multi-bit continuous-time Sigma–Delta modulator with successive-approximation quantizer. In IEEE European Solid-State Circuits Conference, Montreux, Switzerland.

  31. Abo, A., & Gray, P. (1999). A 1.5 V 10-bit 14.3 MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits, 34(5), 599–606.

    Article  Google Scholar 

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Acknowledgements

The authors would like to thank the reviewers for their valuable remarks and suggestions to improve the quality of this paper.

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Authors and Affiliations

  1. IBM Research Laboratories, Zurich, Switzerland

    Jose Bonan & Christoph Hagleitner

  2. University of Pierre and Marie Curie, Paris, France

    Jose Bonan, Hassan Aboushady & Marie-Minerve Louerat

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  1. Jose Bonan
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  2. Christoph Hagleitner
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  3. Hassan Aboushady
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  4. Marie-Minerve Louerat
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Correspondence to Hassan Aboushady.

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Bonan, J., Hagleitner, C., Aboushady, H. et al. Compact and low power ADCs for a MEMS-based probe storage device. Analog Integr Circ Sig Process 76, 23–34 (2013). https://doi.org/10.1007/s10470-013-0067-1

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