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A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

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Abstract

This paper presents a wireless receiver front-end intended for cellular applications implemented in a 65 nm CMOS technology. The circuit features a low noise amplifier (LNA), quadrature passive mixers, and a frequency divider generating 25 % duty cycle quadrature local oscillator (LO) signals. A complementary common-gate LNA is used, and to meet the stringent linearity requirements it employs positive feedback with transistors biased in the sub-threshold region, resulting in cancellation of the third order non-linearity. The mixers are also linearized, using a baseband to LO bootstrap circuit. Measurements of the front-end show about 3.5 dB improvement in out-of-band IIP3 at optimum bias of the positive feedback devices in the LNA, resulting in an out-of-band IIP3 of 10 dBm. With a frequency range from 0.7 to 3 GHz the receiver front-end covers most important cellular bands, with an input return loss above 9 dB and a voltage gain exceeding 16 dB for all bias settings. The circuit consumes 4.38 mA from a 1.5 V supply.

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Acknowledgments

The authors would like to thank the Swedish Foundation for Strategic Research for funding the Digitally Assisted Radio Evolution project, and the other researchers in the Analog RF group at Lund University for fruitful discussions.

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Authors and Affiliations

  1. Department of Electrical and Information Technology, Lund University, Box 118, 221 00, Lund, Sweden

    Anders Nejdel, Markus Törmänen & Henrik Sjöland

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  1. Anders Nejdel
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  2. Markus Törmänen
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  3. Henrik Sjöland
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Correspondence to Anders Nejdel.

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Nejdel, A., Törmänen, M. & Sjöland, H. A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback. Analog Integr Circ Sig Process 74, 49–57 (2013). https://doi.org/10.1007/s10470-012-9962-0

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