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Linear transconductor with flipped voltage follower in 130 nm CMOS

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Abstract

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

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Authors and Affiliations

  1. Electrical Communication Engineering Department, Indian Institute of Science Bangalore, Bangalore, India

    K. R. Ajayan & Navakanta Bhat

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  1. K. R. Ajayan
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  2. Navakanta Bhat
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Correspondence to K. R. Ajayan.

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Ajayan, K.R., Bhat, N. Linear transconductor with flipped voltage follower in 130 nm CMOS. Analog Integr Circ Sig Process 63, 321–327 (2010). https://doi.org/10.1007/s10470-009-9396-5

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  • DOI: https://doi.org/10.1007/s10470-009-9396-5

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