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Design optimization for an SOI MOEMS accelerometer

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Abstract

With optimization being vital, the design optimization of a silicon-on-insulator (SOI) micro-opto-electro-mechanical systems accelerometer is discussed in this paper. This process has enabled a simplistic design that employs double-sided deep reactive ion etching (DRIE) on SOI wafer to be able to attain high sensitivity of 294 µW/G with a calculated proof mass displacement of 0.066 µm/G which was close to ANSYS simulated results of 0.061 µm/G. Optimization has also enabled an in-depth study of the effects of the different variables on the overall performance of the device.

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Acknowledgements

This research was supported by Nanyang Technological University and Temasek Lab@NTU TDP.

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Authors and Affiliations

  1. School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore, Singapore

    Adrian J. T. Teo, Holden King-Ho Li & Yong-Jin Yoon

  2. Queensland Micro- and Nanotechnology Centre, Griffith University, 170 Kessels Road, Brisbane, QLD, 4111, Australia

    Say Hwa Tan

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  1. Adrian J. T. Teo
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  2. Holden King-Ho Li
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  3. Say Hwa Tan
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  4. Yong-Jin Yoon
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Correspondence to Holden King-Ho Li or Yong-Jin Yoon.

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Teo, A.J.T., Li, H.KH., Tan, S.H. et al. Design optimization for an SOI MOEMS accelerometer. Microsyst Technol 24, 465–472 (2018). https://doi.org/10.1007/s00542-017-3370-4

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  • DOI: https://doi.org/10.1007/s00542-017-3370-4

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