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Modular multiplication using the core function in the residue number system

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Applicable Algebra in Engineering, Communication and Computing Aims and scope

Abstract

Modular multiplication can be performed in the residue number system (RNS) using a type of Montgomery reduction. This paper presents an alternative in which RNS modular multiplication are performed by using the core function. All of the intermediate calculations use short wordlength operations within the RNS. This work contributes to the long wordlength modular multiplication operation \(Z = A \times B \mod M\), the basis of many DSPs and public-key cryptosystems.

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References

  1. Akushskii, J., Burcev, V.M., Pak, I.T.: A new positional characteristic of nonpositional codes and its applications. In: Amerbsev, V.M. (ed.) Coding theory and the optimization of complex systems. SSR, Alm-Ata ‘Nauka’ Kazah (1977)

  2. Bajard, J.C., Didier, L.S., Kornerup, P.: Modular multiplication and base extensions in residue number systems. In: Proceedings of 15th IEEE Symposium on Computer Arithmetic, vol. 2, pp. 59–65 (2001)

  3. Barraclough, S.R.: The design and implementation of the ims a110 image and signal processor. In: Proceedings of IEEE CICC, pp. 24.5/1–4, San Diego (1989)

  4. Baugh, C., Wooley, B.: A two’s complement parallel array multiplication algorithm. IEEE Trans. Comput. 22(12), 1045–1047 (1973)

    Article  MATH  Google Scholar 

  5. Philips, Braden, Kong, Yinan, Lim, Z.: Highly parallel modular multiplication in the residue number system using sum of residues reduction. Appl. Algebra Eng. Commun. Comput. 21, 249–255 (2010)

    Article  Google Scholar 

  6. Burgess, N.: Scaled and unscaled residue number system to binary conversion techniques using the core function. In: Proceedings of 13th IEEE Symposium on Computer Arithmetic, pp. 250–257 (1997)

  7. Burgess, N.: Scaling an RNS number using the core function. In: Proceedings of 16th IEEE Symposium on Computer Arithmetic (2003)

  8. Chokshi, R., Berezowski, K.S., Shrivastava, A., Piestrak, S.J.: Exploiting residue number system for power-efficient digital signal processing in embedded processors. In: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems (CASES09), pp. 19–27 (2009)

  9. Dadda, L.: Some schemes for parallel multipliers. Alta Freq. 34, 349–356 (1965)

    Google Scholar 

  10. Dhanesha, H., Falakshahi, K., Horowitz, M.: Array-of-arrays architecture for parallel floating point multiplication. In: Proceedings of Conference on Advanced Research in VLSI, pp. 150–157 (1995)

  11. Elleithy, K., Bayoumi, M.: A massively parallel RNS architecture. In: 25th Asilomar Conference, 1991, Conference Record of the Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 408–412 vol. 1. Institute of Electrical and Electronics Engineers Computer Society, Pacific Grove, CA (1991). doi:10.1109/ACSSC.1991.186482

  12. Gonnella, J.: The application of core functions to residue number systems. IEEE Trans. Signal Process. 39, 284–288 (1991)

    Article  Google Scholar 

  13. Hatamian, M., Cash, G.: A 70-mhz 8-bit \(\times \) 8-bit parallel pipelined multiplier in 2.5-\(\mu \)m cmos. JSSC 21(4), 505–513 (1986)

    Google Scholar 

  14. Hennessy, J., Patterson, D.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Mateo (1990)

    Google Scholar 

  15. Itoh, N., et al.: A 600-mhz 54 \(\times \) 54-bit multiplier with rectangular-styled wallace tree. IEEE J Solid-State Circuits 36(2), 249–257 (2001)

    Article  Google Scholar 

  16. Jenkins, W.K.: Finite Arithmetic Concepts. In: Mitra, S.K., Kaiser, J.F. (eds.) Handbook for Digital Signal Processing, pp. 611–675. Wiley, London (1993)

    Google Scholar 

  17. Kong, Y., Lai, Y.: Low latency modular multiplication for public-key cryptosystems using a scalable array of parallel processing elements. In: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1039–1042 (2013). doi:10.1109/MWSCAS.2013.6674830

  18. Kong, Y., Phillips, B.: Residue number system scaling schemes. In: Al-Sarawi, S.F. (ed.) Proceedings of SPIE, Smart Structures, Devices, and Systems II, vol. 5649, pp. 525–536 (2005)

  19. Miller, D.D., Polky, J.N., King, J.R.: A survey of soviet developments in residue number theory applied to digital filtering. In: Proceedings of the 26th Midwest Symposium on Circuits and Systems (1983)

  20. Mohan, A.: Residue Number Systems: Algorithms and Architectures. Kluwer Academic Pub, Dordrecht (2002)

    Book  Google Scholar 

  21. Mou, Z., Jutand, F.: A class of close-to-optimum adder trees allowing regular and compact layout. In: Proceedings of IEEE International Conference on Computer Design, pp. 251–254 (1990)

  22. Ohkubo, N., et al.: A 4.4 ns cmos 54 \(\times \) 54-bit multiplier using pass-transistor multiplexer. IEEE J Solid-State Circuits 30(3), 251–257 (1995)

    Article  Google Scholar 

  23. Omondi, A., Premkumar, B.: Residue Number Systems—Theory and Implementation, Advances in Computer Science and Engineering: Texts, vol. 2. Imperial College Press, UK (2007)

    Google Scholar 

  24. Orup, H., Kornerup, P.: A high-radix hardware algorithm for calculating the exponential \(m^e\). In: Proceedings of the 10th IEEE Symposium on Computer Arithmetic, vol. 576, pp. 51–57 (1991)

  25. Paliouras, V., Stouraitis, T.: Multifunction architectures for rns processors. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 46(8), 1041–1054 (1999)

    Article  Google Scholar 

  26. Parhami, B.: Computer Arithmetic—Algorithms and Hardware Designs. Oxford University Press, Oxford (2000)

    Google Scholar 

  27. Ramirez, J., Garcia, A., Lopez-Buedo, S., Lloris, A.: Rns-enabled digital signal processor design. Electron. Lett. 38(6), 266–268 (2002)

    Article  Google Scholar 

  28. Richman, F.: Number theory: an introduction to algebra. Contemporary undergraduate mathematics series, Brooks/Cole Publ. Co. (1971)

  29. Santoro, M.: Design and clocking of vlsi multipliers. Ph.d. thesis, Stanford University, CSL-TR-89-397 (1989)

  30. Soderstrand, M.A., Jenkins, W., Jullien, G.: Residue Number System Arithmetic: Modern Applications. IEEE Press, New Jersey (1986)

    MATH  Google Scholar 

  31. Sutherland, I.S., Sproull, B., Harris, D.: Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, San Francisco (1999)

    Google Scholar 

  32. Szabo, N.S., Tanaka, R.H.: Residue Arithmetic and its Applications to Computer Technology. McGraw Hill, New York (1967)

    MATH  Google Scholar 

  33. Wallace, C.: A suggestion for a fast multiplier. IEEE Trans. Electron. Comput. EC–13, 14–17 (1964)

    Article  Google Scholar 

  34. Walter, C.D.: Faster multiplication by operand scaling. In: Advances in Cryptology - Crypto 91. Lecture Notes in Computer Science, vol. 576, pp. 313–323. Springer, Berlin/Heidelberg, Germany (1992)

  35. Weinberger, A.: 4—2 carry-save adder module. IBM Techn. Discl. Bull. 23, 3811–3814 (1981)

    Google Scholar 

  36. Weinberger, A., Smith, J.: A logic for high-speed addition. In: System Design of Digital Computer at the National Bureau of Standards: Methods for High-Speed Addition and Multiplication, Circular 591, vol. 23, chap. 1, pp. 3–12. National Bureau of Standards (1958)

  37. Weste, N., Harris, D.: CMOS VLSI Design—A Circuit and Systems Perspecitive, 3rd edn. Addison Wesley, Boston (2004)

    Google Scholar 

  38. Zuras, D., McAllister, W.: Blalanced delay trees and combinatorial division in vlsi. IEEE J Solid-State Circuits 21(5), 814–819 (1986)

    Article  Google Scholar 

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Correspondence to Shahzad Asif.

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Kong, Y., Asif, S. & Khan, M.A.U. Modular multiplication using the core function in the residue number system. AAECC 27, 1–16 (2016). https://doi.org/10.1007/s00200-015-0268-1

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  • DOI: https://doi.org/10.1007/s00200-015-0268-1

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