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Proof producing synthesis of arithmetic and cryptographic hardware

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Formal Aspects of Computing

Abstract

A compiler from a synthesisable subset of higher order logic to clocked synchronous hardware is described. It is being used to create coprocessors for cryptographic and arithmetic applications. The compiler automatically translates a function f defined in higher order logic (typically using recursion) into a device that computes f via a four-phase handshake circuit. Compilation is by fully automatic proof in the HOL4 system, and generates a correctness theorem for each compiled function. Synthesised circuits can be directly translated to Verilog, and then input to design automation tools. A fully-expansive ‘LCF methodology’ allows users to safely modify and extend the compiler’s theorem proving scripts to add optimisations or to enlarge the synthesisable subset of higher order logic.

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References

  1. Bjesse P, Claessen K, Sheeran M, Singh S (1999) Lava: Hardware design in Haskell. ACM SIGPLAN Notices 34(1):174–184

    Article  Google Scholar 

  2. Blumenröhr C, Eisenbiegler D (1998) Performing high-level synthesis via program transformations within a theorem prover. In: Proceedings of the Digital System Design Workshop at the Euromicro 98 Conference, Västeras, Sweden, pp 34–37, Universität Karlsruhe, Institut für Rechnerentwurf und Fehlertoleranz

  3. Bowen JP, He J (2001) An approach to the specification and verification of a hardware compilation scheme. J Supercomput 19(1):23–39

    Article  MATH  Google Scholar 

  4. Brock B, Hunt Jr WA (1997) The DUAL-EVAL hardware description language and its use in the formal specification and verification of the fm9001 microprocessor. Formal Methods Syst Des 11(1):71–104

    Article  Google Scholar 

  5. Blumenröhr C (1999) A formal approach to specify and synthesize at the system level. In: GI Workshop Modellierung und Verifikation von Systemen. Shaker-Verlag, Braunschweig, Germany, pp 11–20

  6. Chin S-K (1992) Verified functions for generating signed-binary arithmetic hardware. IEEE Trans Comput-Aided Des Integ Circ Syst 11(12):1529–1558

    Article  Google Scholar 

  7. Common criteria for information security evaluation, 2004. Part 3: Security Assurance Requirements, http://niap.nist.gov/ cc-scheme/cc_docs/cc_v22_part3.pdf.

  8. Duan J, Hurd J, Li G, Owens S, Slind K, Zhang J (2005) Functional correctness proofs of encryption algorithms. In: Proceedings of 12th conference on logic for programming artificial intelligence and reasoning (LPAR 2005), number 3835 in LNAI, Springer, Heidelberg, pp 519–533

  9. Finn S, Fourman MP, Francis M, Harris R (1989) Formal system design—interactive synthesis based on computer-assisted formal reasoning. In: Luc Claesen (ed) IMEC-IFIP international workshop on applied formal methods for correct VLSI Design, Vol 1, pp 97–110, Houthalen, Belgium, November 1989. Elsevier Science Publishers, B.V. North-Holland, Amsterdam

  10. Fox A Verifying ARM6 multiplication. http://www.cl.cam.ac.uk/users/acjf3.

  11. Hauck S (1995) Asynchronous design methodologies: an overview. Proc IEEE 83(1):69–93

    Article  Google Scholar 

  12. Herbert JMJ (1988) Temporal abstraction of digital designs. In: George J. Milne (ed) The fusion of hardware design and verification: proceedings of the IFIP WG 10.2 Working conference on the fusion of hardware design and verification: Glasgow, Scotland, North-Holland, pp 4–6

  13. Hanna FK, Longley M, Daeche N (1989) Formal synthesis of digital systems. In: Claesen L. (ed) Applied formal methods for correct VLSI Design, North-Holland, pp 153–170

  14. Hennessy JL, Patterson DA (1992) Computer architecture. A quantitative approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA

    Google Scholar 

  15. Johnson SD, Bose B (1990) DDD—A system for mechanized digital design derivation. Technical Report TR323, Indiana University, IU Computer Science Department

  16. Jones G, Sheeran M (1990) Circuit design in Ruby. In: Staunstrup J. (ed) Formal methods for VLSI design. Elsevier Science Publications, North-Holland, pp 13–70

    Google Scholar 

  17. Jones G, Sheeran M (1990) Circuit design in Ruby. Lecture notes on Ruby from a summer school in Lyngby, Denmark., September

  18. Jones G, Sheeran M (1991) Relations and refinement in circuit design. In: Morgan C. (ed) BCS FACS Workshop on Refinement. Springer, Heidelberg

    Google Scholar 

  19. Melham TF (1993) Higher order logic and hardware verification. Cambridge University Press, Cambridge, England, 1993. Cambridge Tracts in Theoretical Computer Science 31

  20. Mycroft A, Sharp R (2001) Hardware synthesis using SAFL and application to processor design. In: Proceedings of the 11th advanced research working conference on correct hardware design and verification methods (CHARME’01), Livingston, Scotland, September 2001. Springer, Heidelberg. Invited Talk. LNCS Vol 2144

  21. Norrish M, Slind K (project administrators). The HOL4 System. SourceForge website. http://hol.sourceforge.net/.

  22. O’Donnell J (2002) Overview of Hydra: A concurrent language for synchronous digital circuit design. In: Proceedings of the 16th international parallel and distributed processing symposium. IEEE Computer Society Press

  23. Page I (1996) Constructing hardware-software systems from a single description. J VLSI Signal Process 12(1):87–107 citeseer.ist.psu.edu/page96constructing.html

    Article  Google Scholar 

  24. Pnueli A, Siegel M, Singerman E (1998) Translation validation. In: Proceedings of TACAS’98, Vol 1384 of Lecture Notes in Computer Science, Springer, Heidelberg, pp 151–166

  25. Kumar R, Blumenroehr C, Eisenbiegler D, Schmid D (1996) Formal synthesis in circuit design-A classification and survey. In: Srivas M., Camilleri A. (ed) First international conference on formal methods in computer-aided design, Vol 1166. Springer, Heidelberg, pp 294–299, Palo Alto, CA, USA

    Chapter  Google Scholar 

  26. Rivest R, Robshae M, Sidney R, Yin YL(1998) The RC6 block cipher. Available at http://www.rsasecurity.com/rsalabs/rc6, August

  27. Sheeran M (1984) μFP, A language for VLSI design. In: Proceedings of the ACM symposium on LISP and functional programming, ACM Press, Austin, Texas, pp 104–112

  28. Sheeran M (1984) muFP, A language for VLSI design. In: Conference record of the 1984 ACM symposium on lisp and functional programming, ACM, New York, pp 104–112

  29. Slind K (1996) Function definition in higher order logic. In: Theorem proving in higher order logics, number 1125 in lecture notes in computer science, Springer, Heidelberg, pp 381–398, Turku, Finland

  30. Slind K (2000) Wellfounded schematic definitions. In: David McAllester (ed) In: Proceedings of the seventeenth international conference on automated deduction CADE-17, Vol 1831 of Lecture Notes in Computer Science. Springer, Heidelberg, pp 45–63, Pittsburgh, Pennsylvania

  31. van Berkel K(1993) Handshake circuits: an asynchronous architecture for VLSI programming. Cambridge University Press, New York, NY, USA

    MATH  Google Scholar 

  32. Wheeler D, Needham R (1999) TEA, a tiny encryption algorithm. In Fast Software Encryption: Second International Workshop, Vol 1008 of LNCS. Springer, Heidelberg, pp 363–366

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Authors and Affiliations

  1. School of Computing, University of Utah, 50 South Central Campus Drive, Salt Lake City, Utah, UT84112, USA

    Konrad Slind & Scott Owens

  2. University of Cambridge Computer Laboratory, William Gates Building, 15 JJ Thomson Avenue, Cambridge, CB3 0FD, UK

    Juliano Iyoda & Mike Gordon

Authors
  1. Konrad Slind
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  2. Scott Owens
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  3. Juliano Iyoda
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  4. Mike Gordon
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Correspondence to Konrad Slind.

Additional information

R. Lazic, R. Nagarajan and J. C. P. Woodcock

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Slind, K., Owens, S., Iyoda, J. et al. Proof producing synthesis of arithmetic and cryptographic hardware. Form Asp Comp 19, 343–362 (2007). https://doi.org/10.1007/s00165-007-0028-5

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