Abstract
A backward reasoning approach is described to show that the behavioral specification of a finite-state machine satisfies some high-level input-output specification. It is based on the principles of theorem proving. The proof may require inductive reasoning. The theorem prover seeks to find out the properties on which induction needs to be carried out and then proves such properties. Goal-reduction-based backward reasoning is employed. A brief account of the proof procedure is presented. This is followed by an example illustrating the approach. Finally, the approach is presented in an algorithmic form.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Gupta, A.: Formal hardware verification methods: A survey. Technical Report CMU-CS-91-193, Carnegie Mellon University, October 1988.
Browne, M. C., Clarke, E. M., Dill, D. L. and Mishra, B.: Automatic verification of sequential circuits using temporal logic,IEEE Transactions on Computers 35(12) (December 1986), 1035–1044.
Dill, D. L. and Clarke, E. M.: Automatic verification of asynchronous circuits using temporal logic,IEE Proc. 133(5) (September 1986), 276–282.
Wilsey, P. A. and Dasgupta, S.: A formal model of computer architectures for digital system design environment,IEEE Trans. Computer-Aided Design 9(5) (May 1990), 473–486.
Kohavi, Z.:Switching and Finite Automata Theory, Tata-McGraw-Hill Publishing Company, 1978.
Darringer, J. A.: The application of program verification techniques to hardware verification, inProc. ACM/IEEE 16th Design Automation Conf. (June 1979), pp. 375–381.
Bochmann, G. V.: Hardware specification with temporal logic: An example,IEEE Trans. Computers,C-31(3) (March 1982), 223–231.
Gordon, M. J. C.: Why higher order logic is a good formalism for specifying and verifying hardware, Technical Report 77, University of Cambridge (September 1985).
Gordon, M. J. C.: HOL: A proof generating system for higher order logic, Technical Report 103, University of Cambridge (January 1987).
Devadas, S., Ma, T., H.-K. and Newton, A. R.: On the verification of sequential machines at differing levels of abstraction,IEEE Trans. Computer-Aided Design 7(6) (June 1988), 713–722.
Herbert, J.: Formal verification of basic memory devices, Technical Report 124, University of Cambridge (February 1988).
Melham, T. F.: Formalizing abstraction mechanisms for hardware verification in higher order logic, Technical Report 201, University of Cambridge (August 1990).
Nilsson, N. J.:Problem-Solving Methods in Artificial Intelligence, McGraw-Hill, New York, 1971.
Herbert, J.: Case study of the Cambridge fast ring ecl chip using HOL, Technical Report 123, University of Cambridge (February 1988).
Joyce, J. J.: Formal specification and verification of asynchronous processes in higher order logic, Technical Report 136, University of Cambridge (June 1988).
Genesereth, M. R. and Nilsson, N. J.:Logical Foundations of Artificial Intelligence, Morgan Kaufmann Publishers, Inc. (1988).
Barringer, H.: Up and down the temporal way, Technical Report UMCS-85-9-3, University of Manchester (September 1985).
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Chakrabarti, I., Sarkar, D. & Majumdar, A.K. Identification of inductive properties during verification of synchronous sequential circuits. J Autom Reasoning 14, 427–462 (1995). https://doi.org/10.1007/BF00881716
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00881716
Key words
- finite-state machine
- theorem proving
- sequential circuit verification
- goal reduction
- backward reasoning
- inductive reasoning