Skip to main content
SpringerLink
Log in

Hardware architecture for RSA cryptography based on residue number system

  • Published:
Transactions of Tianjin University Aims and scope Submit manuscript

Abstract

A parallel architecture for efficient hardware implementation of Rivest Shamir Adleman (RSA) cryptography is proposed. Residue number system (RNS) is introduced to realize high parallelism, thus all the elements under the same base are independent of each other and can be computed in parallel. Moreover, a simple and fast base transformation is used to achieve RNS Montgomery modular multiplication algorithm, which facilitates hardware implementation. Based on transport triggered architecture (TTA), the proposed architecture is designed to evaluate the performance and feasibility of the algorithm. With these optimizations, a decryption rate of 106 kbps can be achieved for 1 024-b RSA at the frequency of 100 MHz.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Montgomery P L. Modular multiplication without trial division[J]. Mathematics of Computation, 1985, 44(170): 519–521.

    Article  MathSciNet  MATH  Google Scholar 

  2. Wang Dili, Bai Guoqiang, Chen Hongyi. Hardware architecture for the Montgomery multiplication algorithm[J]. Microelectronics and Computer, 2010, 27(5): 1–4(in Chinese).

    MathSciNet  Google Scholar 

  3. Hong Jinhua, Wu Chengwen. Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth’s algorithm[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2003, 11(3): 474–484.

    Article  Google Scholar 

  4. Nozaki Hanae, Motoyama Masahiko, Shimbo Atsushi et al. Implementation of RSA algorithm based on RNS Montgomery multiplication [C]. In: Cryptographic Hardware and Embedded Systems (CHES). Berlin, Germany, 2001. 364–376.

  5. Kawamura Shinichi, Koike Masanobu, Sano Fumihiko et al. Cox-rower architecture for fast parallel Montgomery multiplication[C]. In: Advances in Cryptology-EUROCRYPT 2000. Bruges, Belgium, 2000. 523–538.

  6. Bajard Jean-Claude, Imbert Laurent. A full RNS implementation of RSA [J]. IEEE Transactions on Computers, 2004, 53(6): 769–774.

    Article  Google Scholar 

  7. Qin Baodong, Li Ming, Kong Fanyu. Cryptanalysis of a type of CRT-based RSA algorithms [J]. Journal of Computer Science and Technology, 2008, 23(2): 214–221.

    Article  MathSciNet  Google Scholar 

  8. Cheng Wei, Gu Dawu, Guo Zheng et al. A power analysis attack against RSA-CRT [J]. Communications Technology, 2011, 44(234): 123–128(in Chinese).

    Google Scholar 

  9. Hämäläinen P, Hännikäinen M, Hämäläinen T et al. Implementation of encryption algorithms on transport triggered architectures [C]. In: The 2001 IEEE International Symposium on Circuits and Systems. Sydney, Australia, 2001. 726–729.

  10. Hu Jingwei, Guo Wei, Wei Jizeng et al. A novel architecture for fast RSA key generation based on RNS [C]. In: Fourth International Symposium on Parallel Architectures, Algorithms and Programming (PAAP). Tianjin, China, 2011. 345–349.

  11. Bajard Jean-Claude, Meloni Nicolas, Plantard Thomas. Efficient RNS bases for cryptography [C]. In: World Congress: Scientific Computation Applied Mathematics and Simulation. Paris, France, 2005. 11–15.

  12. Barrett Paul. Implementing the Rivest Shamir and Adleman public key encryption algorithm on a standard digital signal processor [C]. In: Advances in Cryptology — CRYPTO’ 86. Berlin, Germany, 1987. 311–323.

  13. Liu Qiang, Ma Fangzhen, Tong Dong et al. A regular parallel RSA processor [C]. In: 47th IEEE International Midwest Symposium on Circuits and Systems. Hiroshima, Japan, 2004. 467–470.

  14. Shieh Mingder, Chen Junhong, Wu Haohsuan et al. A new modular exponentiation architecture for efficient design of RSA cryptosystem [J]. IEEE Transactions on Very Large Scale Integration(VLSI)Systems, 2008, 16(9): 1151–1161.

    Article  Google Scholar 

  15. Shieh Mingder, Chen Junhong, Lin Wenching et al. A new algorithm for high-speed modular multiplication design [J]. IEEE Transactions on Circuits and Systems-I, 2009, 56(9): 2009–2019.

    Article  MathSciNet  Google Scholar 

  16. Shieh Mingder, Lin Wenching. Word-based Montgomery modular multiplication algorithm for low-latency scalable architectures [J]. IEEE Transactions on Computers, 2010, 59(8): 1145–1151.

    Article  MathSciNet  Google Scholar 

  17. Huang Miaoqing, Gaj Kris, EI-Ghazawi Tarek. New hardware architectures for Montgomery modular multiplication algorithm [J]. IEEE Transactions on Computers, 2011, 60(7): 923–936.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. School of Computer Science and Technology, Tianjin University, Tianjin, 300072, China

    Wei Guo  (郭 炜), Yaling Liu  (刘亚灵), Songhui Bai  (白松辉), Jizeng Wei  (魏继增) & Dazhi Sun  (孙达志)

Authors
  1. Wei Guo  (郭 炜)
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yaling Liu  (刘亚灵)
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Songhui Bai  (白松辉)
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jizeng Wei  (魏继增)
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Dazhi Sun  (孙达志)
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Wei Guo  (郭 炜).

Additional information

Supported by the Natural Science Foundation of Tianjin (No. 11JCZDJC15800), and the National Natural Science Foundation of China (No. 61003306).

GUO Wei, born in 1961, female, Prof.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Guo, W., Liu, Y., Bai, S. et al. Hardware architecture for RSA cryptography based on residue number system. Trans. Tianjin Univ. 18, 237–242 (2012). https://doi.org/10.1007/s12209-012-1902-7

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12209-012-1902-7

Keywords

Search

Navigation