Abstract
This paper presents a self-calibrating dynamic latched comparator that does not require additional static current or load capacitors to reduce its offset voltage. The proposed comparator uses a reconfigurable differential pair at the input stage; the configuration is determined by a digital calibration scheme that automatically matches the differential pair, resulting in a low offset voltage. We present a novel time-domain offset detection technique in the calibration loop, which is based on measuring the metastable time of the comparator. The offset detector uses a ring time-to-digital converter with a simple time amplifier. The proposed comparator was fabricated with standard 180 nm CMOS technology; it achieves a standard deviation of 1.3 mV offset voltage and \(13.5 \,\upmu \hbox {W}\) power consumption with a power supply of 1.5 V.
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Acknowledgments
This work was supported in part by MEXT Grant-in-Aid for Scientific Research 25820141, 25249047 and by CASIO Science Promotion Foundation. We also thank Rohm Corp. and Toppan Printing Corp. with the VLSI Design and Education Center (VDEC), the University of Tokyo, for chip fabrication.
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Okazawa, T., Akita, I. & Ishida, M. A digitally calibrated dynamic comparator using time-domain offset detection. Analog Integr Circ Sig Process 81, 561–570 (2014). https://doi.org/10.1007/s10470-014-0410-1
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DOI: https://doi.org/10.1007/s10470-014-0410-1