, Volume 17, Issue 1, pp 13-27

Parity, circuits, and the polynomial-time hierarchy

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Abstract

A super-polynomial lower bound is given for the size of circuits of fixed depth computing the parity function. Introducing the notion of polynomial-size, constant-depth reduction, similar results are shown for the majority, multiplication, and transitive closure functions. Connections are given to the theory of programmable logic arrays and to the relativization of the polynomial-time hierarchy.

Research partially funded by NSF Grant MCS-81-05555 and ONR Grant N00014-76-C-0370.