Mathematical systems theory

, Volume 17, Issue 1, pp 13–27

Parity, circuits, and the polynomial-time hierarchy

Authors

  • Merrick Furst
    • Department of Computer ScienceCarnegie-Mellon University
  • James B. Saxe
    • Department of Computer ScienceCarnegie-Mellon University
  • Michael Sipser
    • Department of MathematicsMassachusetts Institute of Technology
Article

DOI: 10.1007/BF01744431

Cite this article as:
Furst, M., Saxe, J.B. & Sipser, M. Math. Systems Theory (1984) 17: 13. doi:10.1007/BF01744431

Abstract

A super-polynomial lower bound is given for the size of circuits of fixed depth computing the parity function. Introducing the notion of polynomial-size, constant-depth reduction, similar results are shown for the majority, multiplication, and transitive closure functions. Connections are given to the theory of programmable logic arrays and to the relativization of the polynomial-time hierarchy.

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© Springer-Verlag New York Inc 1984