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Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation

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Abstract

In this paper we present a local interpolation-based variant of the well-known polar format algorithm used for synthetic aperture radar (SAR) image formation. We develop the algorithm to match the capabilities of the application-specific logic-in-memory processing paradigm, which off-loads lightweight computation directly into the SRAM and DRAM. Our proposed algorithm performs filtering, an image perspective transformation, and a local 2D interpolation, and supports partial and low-resolution reconstruction. We implement our customized SAR grid interpolation logic-in-memory hardware in advanced 14 nm silicon technology. Our high-level design tools allow to instantiate various optimized design choices to fit image processing and hardware needs of application designers. Our simulation results show that the logic-in-memory approach has the potential to enable substantial improvements in energy efficiency without sacrificing image quality.

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References

  1. Carrara, W., Goodman, R., Majewski, R. (1995). Spotlight synthetic aperture radar: Signal processing algorithms. Artech House.

  2. McFarlin, D., Franchetti, F., Püschel, M., Moura, J. (2009). High performance synthetic aperture radar image formation on commodity multicore architectures. In SPIE.

  3. Zhu, Q., Turnerz, E.L., Bergery, C.R., Pileggi, L., Franchetti, F. (2011). Application-specific logic-in-memory for polar format synthetic aperture radar. In HPEC.

  4. Zhu, Q., Bergery, C.R., Turnerz, E.L., Pileggi, L., Franchetti, F. (2012). Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory. In ICASSP.

  5. Morris, D., Rovner, V., Pileggi, L., Strojwas, A., Vaidyanathan, K. (2010). Enabling application-specific integrated circuits on limited pattern constructs. In Symp. VLSI technology.

  6. Morris, D., Vaidyanathan, K., Lafferty, N., Lai, K., Liebmann, L., Pileggi, L. (2011). Design of embedded memory and logic based on pattern constructs. In Symp. VLSI technology.

  7. Kogge, P.M., Sunaga, T., Miyataka, H., Kitamura, K., Retter, E. (1995). Combined DRAM and logic chip for massively parallel systems. In Conf. advanced research in VLSI.

  8. Brockman, J.B., Kogge, P.M. (1997). The case for processing-in-memory. IEEE Computer.

  9. Shacham, O., Azizi, O., et al. (2010) Rethinking digital design: Why design must change. IEEE Micro, 30(6): 9–24.

    Article  Google Scholar 

  10. Shacham, O. (2011). Chip multiprocessor generator: automatic generation of custom and heterogeneous compute platforms. PhD thesis, Stanford.

  11. Rudin, J. (2007). Implementation of Polar Format SAR Image Formation on the IBM Cell Broadband Engine. In Proc. HPEC.

  12. Kestur, S., Park, S., Irick, K., Maashri, A., Narayanan, V. (2010). Accelerating the nonuniform fast fourier transform using FPGAs. In FCCM.

  13. Kestur, S., Irick, K., Park, S., Maashri, A., Narayanan, V., Chakrabari, C. (2011). An Algorithm-Architecture Co-design Framework for Gridding Reconstruction using FPGAs. In DAC.

  14. Sorensen, T., Schaeffter, T., Noe, K., Hansen, M. (2008). Accelerating the nonequispaced fast fourier transform on commodity graphics hardware. In IEEE tran. on medical imaging.

  15. Che, S., Li, J., Sheaffer, J.W., Skadron, K., Lach, J. (2008). Accelerating compute-intensive applications with GPUs and FPGA. In SASP.

  16. Kuon, I., Rose, J. (2007). Measuring the Gap between FPGAs and ASICs. In IEEE transactions on computer-aided design of integrated circuits and systems.

  17. Wolberg, G. (1990) Digital image warping (systems). IEEE Computer Society Press.

  18. Lyons, R. (2004). Understanding digital signal processing. Prentice Hall.

  19. Noetzel, A.S. (1989) An interpolating memory unit for function evaluation: analysis and design. IEEE Transactions on Computers, 38(3), 377–384.

    Article  MathSciNet  Google Scholar 

  20. Meijering, E. (2002). A chronology of interpolation: from ancient astronomy to modern signal and image processing. In Proceedings of the IEEE (pp. 319–342).

  21. Williams, L. (1983) Pyramidal parametrics. Computer Graphics, 17(3).

  22. Atkinson, K.A. (1988). An introduction to numerical analysis. Wiley.

  23. Murachi, Y., Kamino, T., Miyakoshi, J., Kawaguchi, H., Yoshimoto, M. (2007). A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing. (Vol. 107 pp. 47–52): IEICE Tech. Rep.

  24. Shacham, O., et al. (2012). Genesis2 chip generator interactive GUI: http://genesis2.stanford.edu/mediawiki/index.php/Main_Page.

  25. Solomatnikov, A., Firoozshahian, A., Qadeer, W., Shacham, O., Kelley, K., Asgar, Z., Wachs, M., Hameed, R., Horowitz, M. (2007). Chip multi-processor generator.

  26. Zhu, Q.L., Vaidyanathan, K., Shachamy, O., Horowitz, M., Pileggi, L., Franchetti, F. (2012). Design automation framework for application-specific logic-in-memory blocks.

  27. Brooks, D., Tiwari, V. (2000). Wattch: a framework for architectural-level power analysis and optimizations.

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Acknowledgments

The authors acknowledge the support of the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity.

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Correspondence to Qiuling Zhu.

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Zhu, Q., Berger, C.R., Turner, E.L. et al. Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation. J Sign Process Syst 71, 297–312 (2013). https://doi.org/10.1007/s11265-012-0720-4

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  • DOI: https://doi.org/10.1007/s11265-012-0720-4

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