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Degree-sequenced matching algorithms for input-queued switches

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Abstract

This paper presents a class of algorithms for scheduling packets in input-queued switches. As opposed to previously known algorithms that focus only on achieving high throughput, these algorithms seek to achieve low average delay without compromising the throughput achieved.

Packet scheduling in input-queued switches based on the virtual-output-queued architecture is a bipartite graph matching problem wherein ports are represented by vertices and the traffic flows by the edges. The set of matched edges determine the packets that are to be transferred from the input ports to the output ports. Current matching algorithms implicitly prioritize high-degree vertices, i.e., ports with a large number of flows, causing longer delays at ports with a smaller number of flows. Motivated by this observation, we present three matching algorithms based on explicitly prioritizing low-degree vertices and the edges through them. Using both real gateway traffic traces as well as synthetically generated traffic, we present simulation results showing that this class of algorithms achieves a low average delay as compared to other scheduling algorithms of equivalent complexity while still achieving similar throughput. We also show that these algorithms determine the maximum size matching in almost all cases.

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References

  1. T.E. Anderson, S.S. Owicki, J.B. Saxe and C.P. Thacker, High-speed switch scheduling for local-area networks. ACM Trans. Comput. Syst. 11(4) (1993) 319–352.

    Article  Google Scholar 

  2. D. Angluin and L.G. Valiant, Fast probabilistic algorithms for hamiltonian circuits and matchings, in: ACM STOC, Boulder, CO, USA (1977), pp. 30–41. ACM Press.

    Google Scholar 

  3. A. Charny, P. Krishna, N. Patel and R. Simcoe, Algorithms for providing bandwidth and delay guarantees in input-buffered crossbars with speedup. in: Proc. 6-th Int’l Wksp. on Quality-of-Service (IWQoS 98), Napa, CA, USA (1998) pp. 235–244.

  4. N. Gura and H. Eberle, The least choice first (lcf) scheduling method for high-speed network switches, in: Proc. IEEE Intl. Parallel and Distributed Processing Symposium, Ft. Lauderdale, FL, USA (2002) pp. 51–60.

  5. Hopcroft and Karp, An \(n^\frac52\) algorithm for maximum matchings in bipartite graphs. SIAM J. on Computing 2(4) (1973) 225.

  6. T. Javidi, R. Magill and T. Hrabik, A high-throughput scheduling algorithm for a buffered crossbar switch fabric. in: Proc. IEEE Int’l Conf. Communications, Vol. 5, Helsinki, Finland (2001) pp. 1586–1591.

  7. A. Kam and K.-Y. Siu, Linear complexity algorithms for QoS support in input-queued switches with no speedup. IEEE J. Select. Areas Commun. 17(6) (1999) 1040–1056.

    Article  Google Scholar 

  8. M. Karol, M. Hluchyj and S. Morgan, Input verses output queueing on a space division packet switch. IEEE Trans. Commun. COM-35 (1987) 1347–1356.

    Google Scholar 

  9. I. Keslassy, R. Zhang-Shen and N. McKeown, Maximum size matching is unstable for any packet switch. IEEE Commun. Lett. 7(10) (2003) 496–498.

    Article  Google Scholar 

  10. E. Leonardi, F. Neri and B. Yener, Algorithms for virtual output queued switching, in: Proc. IEEE GLOBECOM, Vol. 2, Rio de Janeiro, Brasil (1999) pp. 1203–1210.

  11. N. McKeown, iSLIP: A scheduling algorithm for input-queued switches. IEEE/ACM Trans. Networking 7(2) (1999) 188–201.

    Google Scholar 

  12. N. McKeown, A. Mekkittikul, V. Anantharam and J. Walrand, Achieving 100% throughput in an input-queued switch. IEEE Trans. Commun. 47(8) (1999) 1260–1267.

    Article  Google Scholar 

  13. N. Ni and L.N. Bhuyan, Fair scheduling in internet routers. IEEE Trans. on Comput., Special Issue on Quality of Service Issues in Internet Web Services 51(6) (2002) 686–701.

    Google Scholar 

  14. NLANR Colorado State University OC3c tap (2003, Nov.). COS-1069192584-1.tsh.gz. NLANR Colorado State University OC3c tap. [Available on Request.].

  15. M. Shreedhar and G. Varghese, Efficient fair queueing using deficit round-robin. IEEE/ACM Trans. on Networking 4(3) (1996) pp. 275–285.

    Google Scholar 

  16. Y. Tamir and G.L. Frazier, High-performance multi-queue buffers for vlsi communications switches, in: Proc. 15-th Annual Int’l Symp. on Comp. Arch. (ISCA), Honolulu, Hawaii, USA (1988) pp. 343–354.

  17. X. Zhang and L. Bhuyan, Deficit round robin scheduling for input queued switches. IEEE J. Select. Areas Commun., Special Issue on High Performance Optical/Electronic Switches/Routers for High Speed Internet 21(4) (2003) 584–594.

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Authors and Affiliations

  1. Computer Communications Laboratory, Department of Electrical and Computer Engineering, Drexel University, 3141 Chestnut Street, Philadelphia, PA, 19104-2875, USA

    Madhusudan Hosaagrahara & Harish Sethu

Authors
  1. Madhusudan Hosaagrahara
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  2. Harish Sethu
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Correspondence to Madhusudan Hosaagrahara.

Additional information

This work was supported in part by NSF CAREER Award CCR-9984161.

A preliminary version of this paper was presented at the 2005 IEEE Int’l Conference on Computer Communications and Networks, San Diego, USA.

Madhusudan Hosaagrahara received the B.Tech degree in electrical engineering from the Indian Institute of Technology (IIT), Kharagpur in 2000 and the Ph.D. degree in electrical engineering from Drexel University in 2006. His research interests include design, analysis and implementation of computer systems and networks with emphasis on performance and quality-of-service. He is a member of IEEE, ACM and SIAM.

Harish Sethu obtained his B.Tech in Electronics and Communication Engineering from Indian Institute of Technology (IIT), Chennai in 1988. He received his Ph.D. in Electrical Engineering from Lehigh University in 1992. Prior to joining Drexel University, he was an Advisory Development Engineer/Scientist at the RS/6000 SP Division of IBM Corporation where he contributed to the hardware, software and system-level design of more than two generations of the SP family of high-performance parallel computers. He was a recipient of the NSF CAREER award in the year 2000. He is a member of IEEE, ACM, AMS and SIAM. His current research interests are in the design and analysis of protocols, architectures and algorithms in computer networks with emphasis on distributed algorithms in computer networks, quality-of-service, large-scale dynamics of the Internet, network security, mobile ad hoc networks and sensor networks.

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Hosaagrahara, M., Sethu, H. Degree-sequenced matching algorithms for input-queued switches. Telecommun Syst 34, 37–49 (2007). https://doi.org/10.1007/s11235-006-9024-y

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