Abstract
This study investigates fluid–structure interaction (FSI) analysis of stacked chip in the encapsulation of molded underfill packaging using ANSYS Coupling Work bench with fluid and structural solvers. During encapsulation, FSI analysis is applied to a molded package with different layouts, namely cases 1–4 of stacked chip. An even ratio of inlet and outlet gate pressures is used to produce a regular melt front advancement. An experimental setup is fabricated to validate the simulation results in the FSI study. A digital camera is used to capture the melt front advancement and structural deformation. The interaction between structures (silicon chip) and epoxy molding compound (EMC) is displayed in the displacement profile. Maximum deformation is evaluated during the final stage of filling. The silicon die experiences von Mises stresses, which are monitored to observe the risk of die cracking. The results of this study showed that, the EMC flow front advancement was the fastest in case 4. The pressure distribution of each case was nearly identical, and the maximum von Mises stress was distributed unevenly at the middle of the stacked chip. The proposed analysis can serve as a reference and guide in designing and improving 3D integration packages in industry.
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Hon, R.; Lee, S.W.R.; Zhang, S.X.; Wong, C.K.: Multistack flip chip 3D packaging with copper plated through-silicon vertical interconnection. 2005 7th Electron. Packag. Technol. Conf. 2, 384–389 (2005)
Farooq, M.; Iyer, S.: 3D integration review. Sci. China Inf. Sci. 54, 1012–1025 (2011)
Davis, W.R.; Wilson, J.; Mick, S.; Xu, J.; Hua, H.; Mineo, C.; Sule, A.M.; Steer, M.; Franzon, P.D.: Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des. Test Comput. 22, 498–510 (2005)
Abdullah, M.K.; Abdullah, M.Z.; Kamarudin, S.; Ariff, Z.M.: Study of flow visualization in stacked-chip scale packages (S-CSP). Int. Commun. Heat Mass Transf. 34, 820–828 (2007)
Bae, D.H.; Lee, M.C.; Lee, E.S.; Yun, H.C.; Lim, J.C.; Kim, I.B.: Simulation of encapsulation process for BGA type semi-conducting microchip. IEEE Trans. Compo. Packag. Technol. 27, 200–209 (2003)
Khor, C.Y.; Abdullah, M.Z.; Ariff, Z.M.; Leong, W.C.: Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package. Int. Commun. Heat Mass Transf. 39, 670–680 (2012)
Wang, H.; Zhou, H.; Zhang, Y.; Li, D.: Stabilized filling simulation of microchip encapsulation process. Microelectron. Eng. 87, 2602–2609 (2010)
Teng, S.Y.; Hwang, S.J.: Simulations and experiments of three-dimensional paddle shift for IC packaging. Microelectron. Eng. 85, 115–125 (2008)
Jong, W.R.; Chen, Y.R.; Kuo, T.H.: Wire density in CAE analysis of high pin-count IC packages: simulation and verification. Int. Commun. Heat Mass Transf. 32, 1350–1359 (2005)
Chang, R.Y.; Yang, W.H.; Hwang, S.J.; Su, F.: Three-dimensional modeling of mold filling in microelectronics encapsulation process. IEEE Trans. Components Packag. Technol. 27, 200–209 (2004)
Schreier-Alt, T.; Rehme, F.; Ansorge, F.; Reichl, H.: Simulation and experimental analysis of large area substrate overmolding with epoxy molding compounds. Microelectron. Reliab. 51, 668–675 (2011)
Nguyen, L.; Quentin, C.; Lee, W.; Bayyuk, S.; Bidstrup-Allen, S.a; Wang, S.-T.: Computational modeling and validation of the encapsulation of plastic packages by transfer molding. J. Electron. Packag. 122, 138 (2000)
Wan, J.W.; Zhang, W.J.; Bergstrom, D.J.: An analytical model for predicting the underfill flow characteristics in flip-chip encapsulation. IEEE Trans. Adv. Packag. 28, 481–487 (2005)
Braun, T.; Wunderle, B.; Becker, K.F.; Koch, M.; Bader, V.; Aschenbrenner, R.; Reichl, H.: Improved reliability of leadfree flip chip assemblies using direct underfilling by transfer molding. In: Proceedings of IEEE/CPMT International Electronics Manufacturing and Technology Symposium, pp. 27–34 (2006)
Zhang, J.; Buckley, M.; Perabo, C.; Todd, M.: Molding compound and underfill material sets for A molded flip-chip SIP package. In: 2005 6th International Conference on Electronics Packaging Technology, pp. 0–4 (2005)
Abdul Aziz, M.S.; Abdullah, M.Z.; Khor, C.Y.; Jalar, A.; Bakar, M.A.; Yusoff, W.Y.W.; Che Ani, F.; Yan, N.; Zhou, M.; Cheok, C.: Implications of adjustable fountain wave in pin through hole soldering process. Arab. J. Sci. Eng. 39, 9101–9111 (2014)
Ani, F.C.; Jalar, A.; Ismail, R.; Othman, N.K.; Abdullah, M.Z.; Aziz, M.S.A.; Khor, C.Y.; Bakar, M.A.: Reflow optimization process: thermal stress using numerical analysis and intermetallic spallation in backwards compatibility solder joints. Arab. J. Sci. Eng. 40, 1669–1679 (2015)
Yang, H.Q.; Bayyuk, S. a.; Nguyen, L.T.: Time-accurate, 3-D computation of wire sweep during plasticencapsulation of IC components. In: 1997 Proceedings of 47th Electronic Components and Technology Conference, pp. 831–836 (1997)
Ramdan, D.; Abdullah, M.Z.; Yusop, N.M.: Effects of outlet vent arrangement on air traps in stacked-chip scale package encapsulation. Int. Commun. Heat Mass Transf. 39, 405–413 (2012)
Shen, Y.K.; Ju, C.M.; Shie, Y.J.; Chien, H.W.: Resin flow characteristics of underfill process on flip chip encapsulation. Int. Commun. Heat Mass Transf. 31, 1075–1084 (2004)
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Ishak, M.H.H., Abdullah, M.Z., Aziz, M.S.A. et al. Study on the Fluid–Structure Interaction at Different Layout of Stacked Chip in Molded Packaging. Arab J Sci Eng 42, 4743–4757 (2017). https://doi.org/10.1007/s13369-017-2659-z
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DOI: https://doi.org/10.1007/s13369-017-2659-z