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High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

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Abstract

We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (∼108), low drain-induced barrier lowering (∼30 mV) and low subthreshold swing (∼80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (∼148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.

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References

  1. Cui, Y.; Wei, Q.; Park, H.; Lieber, C. M. Nanowire nano-sensors for highly sensitive and selective detection of biological and chemical species. Science 2001, 293, 1289–1292.

    Article  CAS  Google Scholar 

  2. McAlpine, M. C.; Ahmad, H.; Wang, D.; Heath, J. R. Highly ordered nanowire arrays on plastic substrates for ultrasensitive flexible chemical sensors. Nat. Mater. 2007, 6, 379–384.

    Article  CAS  Google Scholar 

  3. Boukai, A. I.; Bunimovich, Y.; Tahir-Kheli, J.; Yu, J. -K.; Goddard III, W. A.; Heath, J. R. Silicon nanowires as efficient thermoelectric materials. Nature 2008, 451, 168–171.

    Article  CAS  Google Scholar 

  4. Yu, J. -K.; Mitrovic, S.; Tham, D.; Varghese, J.; Heath, J. R. Reduction of thermal conductivity in phononic nanomesh structures. Nat. Nanotechnol. 2010, 5, 718–721.

    Article  CAS  Google Scholar 

  5. Tian, B.; Zheng, X.; Kempa, T. J.; Fang, Y.; Yu, N.; Yu, G.; Huang, J.; Lieber, C. M. Coaxial silicon nanowires as solar cells and nanoelectronic power sources. Nature 2007, 449, 885–890.

    Article  CAS  Google Scholar 

  6. Singh, N.; Buddharaju, K. D.; Manhas, S. K.; Agarwal, A.; Rustagi, S. C.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. L. Si, SiGe nanowire devices by top-down technology and their applications. IEEE T. Electron. Dev. 2008, 55, 3107–3118.

    Article  CAS  Google Scholar 

  7. Hsu, H. -H.; Liu, T. -W.; Chan, L.; Lin, C. D.; Huang, T. -Y.; Lin, H. -C. Fabrication and characterization of multiplegated poly-Si nanowire thin-film transistors and impacts of multiple-gate structures on device fluctuations. IEEE T. Electron. Dev. 2008, 55, 3063–3069.

    Article  CAS  Google Scholar 

  8. Yan, R. H.; Ourmazd, A.; Lee, K. F. Scaling the Si MOSFET: From bulk to SOI to bulk. IEEE T. Electron. Dev. 1992, 39, 1704–1710.

    Article  CAS  Google Scholar 

  9. Suzuki, K.; Tanaka, T.; Tosaka, Y.; Horie, H.; Arimoto, Y. Scaling theory for double-gate SOI MOSFET’s. IEEE T. Electron. Dev. 1993, 40, 2326–2329.

    Article  CAS  Google Scholar 

  10. Auth, C. P.; Plummer, J. D. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET’s. IEEE Electr. Device Lett. 1997, 18, 74–76.

    Article  Google Scholar 

  11. Yu, B.; Wang, L.; Yuan, Y.; Asbeck, P. M.; Taur, Y. Scaling of nanowire transistors. IEEE T. Electron. Dev. 2008, 55, 2846–2858.

    Article  CAS  Google Scholar 

  12. Wang, D.; Sheriff, B. A.; Heath, J. R. Complementary symmetry silicon nanowire logic: Power-efficient inverters with gain. Small 2006, 2, 1153–1158.

    Article  CAS  Google Scholar 

  13. Asenov, A.; Brown, A. R.; Davies, J. H.; Kaya, S.; Slavcheva, G. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs. IEEE T. Electron. Dev. 2003, 50, 1837–1852.

    Article  CAS  Google Scholar 

  14. Collaert, N.; Dixit, A.; Goodwin, M.; Anil, K. G.; Rooyackers, R.; Degroote, B.; Leunissen, L. H. A.; Veloso, A.; Jonckheere, R.; De Meyer, K.; Jurczak, M.; Biesemans, S. A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node. IEEE Electr. Device Lett. 2004, 25, 568–570.

    Article  CAS  Google Scholar 

  15. Friedman, R. S.; McAlpine, M. C.; Ricketts, D. S.; Ham, D.; Lieber, C. M. High-speed integrated nanowire circuits. Nature 2005, 434, 1085.

    Article  CAS  Google Scholar 

  16. Nam, S.; Jiang, X.; Xiong, Q.; Ham, D.; Lieber, C. M. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits. PNAS 2009, 106, 21035–21038.

    Article  CAS  Google Scholar 

  17. Chen, Z.; Appenzeller, J.; Lin, Y. M.; Sippel-Oakley, J.; Rinzler, A. G.; Tang, J.; Wind, S. J.; Solomon, P. M.; Avouris, P. An integrated logic circuit assembled on a single carbon nanotube. Science 2006, 311, 1735.

    Article  CAS  Google Scholar 

  18. Javey, A.; Wang, Q.; Ural, A.; Li, Y.; Dai, H. Carbon nanotube transistor arrays for multistage complementary logic and ring oscillators. Nano Lett. 2002, 2, 929–932.

    Article  CAS  Google Scholar 

  19. Melosh, N. A.; Boukai, A.; Diana, F.; Gerardot, B.; Badolato, A.; Petroff, P. M.; Heath, J. R. Ultrahigh-density nanowire lattices and circuits. Science 2003, 300, 112–115.

    Article  CAS  Google Scholar 

  20. Heath, J. R. Superlattice nanowire pattern transfer (SNAP). Acc. Chem. Res. 2008, 41, 1609–1617.

    Article  CAS  Google Scholar 

  21. Green, J. E.; Choi, J. W.; Boukai, A.; Bunimovich, Y.; Johnston-Halperin, E.; Delonno, E.; Luo, Y.; Sheriff, B. A.; Xu, K.; Shin, Y. S.; Tseng, H. -R.; Stoddart, J. F.; Heath, J. R. A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre. Nature 2007, 445, 414–417.

    Article  CAS  Google Scholar 

  22. Wang, D.; Bunimovich, Y.; Boukai, A.; Heath J. R. Two-dimensional single-crystal nanowire arrays. Small 2007, 3, 2043–2047.

    Article  CAS  Google Scholar 

  23. Wolf, S. MOS devices and NMOS process integration. In Silicon Processing for the VLSI Era Volume 2 — Process Integration; Lattice Press: California, 1990; p. 317.

    Google Scholar 

  24. Seo, K.; Sharma, S.; Yasseri, A. A.; Stewart, D. R.; Kamins, T. I. Surface charge density of unpassivated and passivate metal-catalyzed silicon nanowires. Electrochem. Solid State Lett. 2006, 9, G69–G72.

    Article  CAS  Google Scholar 

  25. Tham, D.; Heath, J. R. Ultradense, deep subwavelength nanowire array photovoltaics as engineered optical thin films. Nano Lett. 2010, 10, 4429–4434.

    Article  CAS  Google Scholar 

  26. Schroder, D. K. Mobility. In Semiconductor Material and Device Characterization; John Wiley & Sons: New York, 1998; pp. 540–548.

    Google Scholar 

  27. Rudenko, T.; Collaert, N.; De Gendt, S.; Kilchytska, V.; Jurczak, M.; Flandre, D. Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode. Microelectron. Eng. 2005, 80, 386–389.

    Article  CAS  Google Scholar 

  28. van Dal, M. J. H.; Collaert, N.; Doornbos, G.; Vellianitis, G.; Curatola, G.; Pawlak, B. J.; Duffy, R.; Jonville, C.; Degroote, B.; Altamirano E., et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography. In 2007 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 2007, pp. 110–111.

  29. Zheng, G.; Lu, W.; Jin, S.; Lieber, C. M. Synthesis and fabrication of high-performance n-type silicon nanowire transistors. Adv. Mater. 2004, 16, 1890–1893.

    Article  CAS  Google Scholar 

  30. Duan, X.; Niu, C.; Sahi, V.; Chen, J.; Parce, J. W.; Empedocles, S.; Goldman, J. L. High-performance thin-film transistors using semiconductor nanowires and nanoribbons. Nature 2003, 425, 274–278.

    Article  CAS  Google Scholar 

  31. Sun, S. C.; Plummer, J. D. Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces. IEEE J. Solid-State Circ. 1980, 15, 562–573.

    Article  Google Scholar 

  32. Sze, S. M. MOSFET. In Physics of Semiconductor Devices; 2nd ed.; Wiley: New York, 1981; p. 447.

    Google Scholar 

  33. Triyoso, D; Liu, R.; Roan, D; Ramon, M.; Edwards, N. V.; Gregory, R.; Werho, D.; Kulik, J.; Tam, G.; Irwin, E., et al. Impact of deposition and annealing temperature on material and electrical characteristics of ALD HfO2. J. Electrochem. Soc. 2004, 151, F220–227.

    Article  CAS  Google Scholar 

  34. Conley, J. F.; Ono, Y.; Tweet, D. J.; Zhuang, W.; Solanki, R. Atomic layer deposition of thin hafnium oxide films using a carbon free precursor. J. Appl. Phys. 2003, 93, 712–718.

    Article  CAS  Google Scholar 

  35. Onishi, K.; Kang, C. S.; Choi, R.; Cho, H. -J.; Gopalan, S.; Nieh, R. E.; Krishnan, S. A.; Lee, J. C. Improvement of surface carrier mobility of HfO2 MOSFETs by high-temperature forming gas annealing. IEEE T. Electron. Dev. 2003, 50, 384–390.

    Article  CAS  Google Scholar 

  36. Richter, C. A.; Xiong, H. D.; Zhu, X.; Wang, W.; Stanford, V. M.; Hong, W. -K.; Lee, T.; Ioannou, D. E.; Li, Q. Metrology for the electrical characterization of semiconductor nanowires. IEEE T. Electron. Dev. 2008, 55, 3086–3095.

    Article  CAS  Google Scholar 

  37. Rustagi, S. C.; Singh, N.; Fang, W. W.; Buddharaju, K. D.; Omampuliyur, S. R.; Teo, S. H. G.; Tung, C. H.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. L. CMOS inverter based on gate-all-around silicon-nanowire MOSFETs fabricated using top-down approach. IEEE Electr. Device Lett. 2007, 28, 1021–1024.

    Article  CAS  Google Scholar 

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Correspondence to James R. Heath.

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Huang, RG., Tham, D., Wang, D. et al. High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors. Nano Res. 4, 1005–1012 (2011). https://doi.org/10.1007/s12274-011-0157-2

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