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Temperature-dependent C-V characteristics of Au/ZnO/n-Si device obtained by atomic layer deposition technique

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Abstract

Since the importance of Schottkky devices, Au/ZnO/n-Si device were obtained, and the capacitance–voltage (C-V) and conductance-voltage (G-V) characteristics of Au/ZnO/n-Si device were studied using admittance spectroscopy at changing temperature from 160 to 340 K with 20 K intervals and −1 to +2 V bias voltage range. The interface thin film ZnO layer was deposited on the n-type Si wafer by atomic layer deposition technique (ALD) in order to obtain homogenous interface layer. The layer thickness of ZnO was taken as 10 nm by the resulting ZnO film growth rate at about 1.45 Å per cycle. This thin film layer was characterized with XRD and AFM analyses. It can be seen from the C-V curves of the device that the capacitance values increased in depletion region with increasing temperature and exhibited peaks towards to forward biases after 240 K temperature. The changing of capacitance values confirmed re-ordering and re-structuring of charges in the interface of the device with changing temperature. The G-V curves of the device also increased with increasing temperature and towards to forward bias voltages due to increasing free charges in the interface. The series resistance (\({R}_{s}\)) of the device was taken into account to understand its effect on main electrical parameters, and it could be seen from these results that the \({R}_{s}\) strongly depends on the device temperature. The impedance (Z) values decreased with changing from −1 to +2 V bias voltages and increasing temperature. The barrier height which was obtained from the C 2 -V plots increased a slope of 0.00108 eV/K with a decrease in temperature from 160 to 340 K. It can be concluded that the Au/ZnO/n-Si device may be used and improved for next technological applications such as capacitor and memristor.

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Kocyigit, A., Orak, I., Aydoğan, Ş. et al. Temperature-dependent C-V characteristics of Au/ZnO/n-Si device obtained by atomic layer deposition technique. J Mater Sci: Mater Electron 28, 5880–5886 (2017). https://doi.org/10.1007/s10854-016-6261-z

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