Rafal Baranowski, Michael A. Kochte and Hans-Joachim Wunderlich, “Access Port Protection for Reconfigurable Scan Networks,” Journal of Electronic Testing Theory and Applications, volume 30, number 6, pp. 711–723, December 2014.

Abstract: Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG) provide a cost-effective access mechanism for test, reconfiguration, and debugging purposes. The improved accessibility of on-chip instruments, however, poses a serious threat to system safety and security. While state-of-the-art protection methods for scan architectures compliant with JTAG and SECT are very effective, most of these techniques face scalability issues in reconfigurable scan networks allowed by the upcoming IJTAG standard. This paper describes a scalable solution for multi-level access management in reconfigurable scan networks. The access to protected instruments is restricted locally at the interface to the network. The access restriction is realized by a sequence filter that allows only a precomputed set of scan-in access sequences. This approach does not require any modification of the scan architecture and causes no access time penalty. Therefore, it is well suited for core-based designs with hard macros and 3D integrated circuits. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of registers in the network.

Rafal Baranowski Michael A. Kochte Hans-Joachim Wunderlich.

M. A. Kochte and H.-J. Wunderlich are with Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, 70,569 Stuttgart, Germany.

R. Baranowski, previously at the above address, is now with Robert Bosch GmbH, Automotive Electronics, Engineering Integrated Circuits, Tübinger Str. 123, 72,762 Reutlingen, Germany.