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A robust and low-power near-threshold SRAM in 10-nm FinFET technology

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Abstract

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation.

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Authors and Affiliations

  1. Department of Computer Engineering, Sharif University of Technology, Tehran, 111559517, Iran

    Sina Sayyah Ensan & Shaahin Hessabi

  2. Faculty of Electrical Engineering, Shahid Beheshti University G.C., Tehran, 1983963113, Iran

    Mohammad Hossein Moaiyeri

Authors
  1. Sina Sayyah Ensan
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  2. Mohammad Hossein Moaiyeri
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  3. Shaahin Hessabi
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Correspondence to Mohammad Hossein Moaiyeri.

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Ensan, S.S., Moaiyeri, M.H. & Hessabi, S. A robust and low-power near-threshold SRAM in 10-nm FinFET technology. Analog Integr Circ Sig Process 94, 497–506 (2018). https://doi.org/10.1007/s10470-018-1107-7

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  • DOI: https://doi.org/10.1007/s10470-018-1107-7

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