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A 7.9 μA multi-step phase-domain ADC for GFSK demodulators

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Abstract

The phase-domain analog-to-digital converter (Ph-ADC) is proved to be more power efficient than traditional amplitude ADCs in wireless receivers . A low power multi-step Ph-ADC for zero intermediate frequency (IF) GFSK receivers as defined in Bluetooth low energy protocol is proposed in this paper. With dedicatedly designed binary code scheme and multi-step operation, the Ph-ADC requires only 52 current elements and one comparator, in contrast to the design in literature using 260 current elements and 8 comparators. Non-idealities due to transconductance errors and offset errors are theoretically analyzed, followed by a design strategy to minimize trip point errors. Simulation results show that the digital intensive Ph-ADC consumes only 7.9 μA current from a 1.8 V supply when implemented in a 180 nm CMOS process. Monte-Carlo simulations show that the maximum trip point error is only 2.3°, which is less than 1/8 least significant bit. When the Ph-ADC is used in a GFSK demodulator, the required IF Eb/N0 is 13.5 dB to achieve a bit error rates of 0.1%.

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Acknowledgments

This work was supported, in part, by NSFC under contract number 61474070 and 61431166002, and the Okawa Foundation.

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Authors and Affiliations

  1. Tsinghua National Laboratory for Information Science and Technologies, Institute of Microelectronics, Tsinghua University, Beijing, China

    Shaoquan Gao, Hanjun Jiang, Zhaoyang Weng, Yanshu Guo, Jingjing Dong, Fule Li & Zhihua Wang

  2. Research Institute of Tsinghua University, Shenzhen, Guangdong, China

    Yanshu Guo

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  1. Shaoquan Gao
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  2. Hanjun Jiang
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  3. Zhaoyang Weng
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  4. Yanshu Guo
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  5. Jingjing Dong
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  6. Fule Li
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  7. Zhihua Wang
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Correspondence to Hanjun Jiang.

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Gao, S., Jiang, H., Weng, Z. et al. A 7.9 μA multi-step phase-domain ADC for GFSK demodulators. Analog Integr Circ Sig Process 94, 49–63 (2018). https://doi.org/10.1007/s10470-017-1081-5

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  • DOI: https://doi.org/10.1007/s10470-017-1081-5

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