Abstract
A low jitter frequency multiplier, which requires less power, area, and design complexity than reference multiplying PLL or DLL circuits can be used to generate the reference frequency for a low phase noise frequency synthesizer. This paper proposes a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop with coarse and fine delay resolution to generate a \(90^{\circ }\) phase shifted clock that is used to produce a doubled frequency signal with 50% duty cycle. This method can be used to multiply the input frequency of 40 MHz by multiples of 2, up to 16. The design is implemented in 65 nm UMC CMOS process. Operating from 1.2-V supply, it dissipates 0.46 to 1.2 mA at output frequencies 80–640 MHz, achieving − 162.3 and − 139 dBc/Hz phase noise at 1 MHz offset, respectively.
References
Shu, G., Choi, W.-S., Saxena, S., Anand, T., Elshazly, A., & Hanumolu, P. K. (2014). 8.7 a 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65 nm CMOS. In 2014 IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 150–151). IEEE.
Park, D., & Cho, S. (2012). A 14.2 mW 2.55-to-3 GHz cascaded PLL with reference injection and 800 MHz delta-sigma modulator in 0.13 \(\mu \text{ m }\) CMOS. IEEE Journal of Solid-State Circuits, 47(12), 2989–2998.
Banerjee, D. (2006). PLL performance, simulation and design. Dog Ear Publishing.
Ghahramani, M. M., Rajavi, Y., Khalili, A., Kavousian, A., Kim, B., & Flynn, M. P. (2015). A 192 MHz differential XO based frequency quadrupler with sub-picosecond jitter in 28 nm CMOS. In IEEE radio frequency integrated circuits symposium (RFIC), 2015 (pp. 59–62). IEEE.
Huh, H., Koo, Y., Lee, K.-Y., Ok, Y., Lee, S., Kwon, D., et al. (2005). Comparison frequency doubling and charge pump matching techniques for dual-band \({\Delta }\sum\) fractional-N frequency synthesizer. IEEE Journal of Solid-State Circuits, 40(11), 2228–2236.
Park, P., Park, J., Park, H., & Cho, S. (2012). An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. In 2012 IEEE international solid-state circuits conference (pp. 336–337). IEEE.
Abdollahi-Alibeik, S., Weber, D., Dogan, H., Si, W.W., Baytekin, B., Komijani, A., Chang, R., Vakili-Amini, B., Lee, M., Gan, H. et al. (2011). A 65 nm dual-band 3-stream 802.11 n MIMO WLAN SoC. In IEEE international solid-state circuits conference digest of technical papers (ISSCC), 2011 (pp. 170–172). IEEE.
Huh, H., Koo, Y., Lee, K.-Y., Ok, Y., Lee, S., Kwon, D., Lee, J., Park, J., Lee, K., Jeong, D.-K. et al. (2004). A CMOS dual-band fractional-N synthesizer with reference doubler and compensated charge pump. In IEEE international solid-state circuits conference, 2004. Digest of technical papers. ISSCC. 2004 (pp. 100–516). IEEE.
Lee, C. P., Behzad, A., Marholev, B., Magoon, V., Bhatti, I., Li, D., Bothra, S., Afsahi, A., Ojo, D., Roufoogaran, R. et al. (2010). A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier. In 2010 IEEE international solid-state circuits conference-(ISSCC).
Albittar, I. F., & Dogan, H. (2017). A novel technique for duty cycle correction for reference clocks in frequency synthesizers. Microelectronics Journal, 67, 176–182.
Yan, W. S., & Luong, H. C. (2001). A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers. IEEE Journal of Solid-State Circuits, 36(2), 204–216.
ETSI, L. (2013). Evolved universal terrestrial radio access (E-UTRA); user equipment (UE) radio transmission and reception. In 3GPP TS 36.101 version 11.5.0 Release 11).
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Albittar, I.F.I., Dogan, H. A frequency multiplier for reference frequency in frequency synthesizer systems. Analog Integr Circ Sig Process 94, 147–154 (2018). https://doi.org/10.1007/s10470-017-1075-3
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DOI: https://doi.org/10.1007/s10470-017-1075-3