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Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

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Abstract

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a − 10.8 dBm IIP3 with a power consumption of 0.9 mW.

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Acknowledgements

This work was supported by the National Science Foundation under Award No. 1451213.

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Author notes

  1. Chun-hsiang Chang

    Present address: OmniVision Technologies, Santa Clara, CA, USA

  2. Li Xu

    Present address: University of Michigan, Ann Arbor, MI, USA

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Northeastern University, 409 Dana Research Center, Boston, MA, 02115, USA

    Chun-hsiang Chang, Li Xu & Marvin Onabajo

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  1. Chun-hsiang Chang
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  2. Li Xu
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Correspondence to Marvin Onabajo.

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Chang, Ch., Xu, L. & Onabajo, M. Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation. Analog Integr Circ Sig Process 94, 335–346 (2018). https://doi.org/10.1007/s10470-017-1060-x

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