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An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

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Abstract

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.

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Acknowledgements

This work was supported by Inje University Grant 2016 and Human Resource Training Program for Regional Innovation and Creativity, through the Ministry of Education and National Research Foundation of Korea (NRF-2014H1C1A1066686).

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Authors and Affiliations

  1. Department of Nanoscience and Engineering, Center for Nano Manufacturing, Inje University, Gimhae, 621-749, Korea

    Sandeep Kumar, Jinwong Choi & Hanjung Song

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  1. Sandeep Kumar
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  2. Jinwong Choi
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  3. Hanjung Song
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Correspondence to Hanjung Song.

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Kumar, S., Choi, J. & Song, H. An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique. Analog Integr Circ Sig Process 92, 141–149 (2017). https://doi.org/10.1007/s10470-017-0983-6

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  • DOI: https://doi.org/10.1007/s10470-017-0983-6

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