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An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

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Abstract

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm2. The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm2 fJ/conversion-step.

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Acknowledgments

The authors would like to thank the Mixed-signal Microelectronics group in Eindhoven University of Technology, The Netherlands for their support in measurements. This work is financially supported by the Research Council of Norway through the project Microsystems for Medical Ultrasound Video Cameras (192456).

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Authors and Affiliations

  1. Department of Electronics and Telecommunication, Norwegian University of Science and Technology, Trondheim, Norway

    Ye Xu & Trond Ytterdal

  2. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands

    Pieter Harpe

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  1. Ye Xu
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  2. Pieter Harpe
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  3. Trond Ytterdal
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Correspondence to Ye Xu.

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Xu, Y., Harpe, P. & Ytterdal, T. An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS. Analog Integr Circ Sig Process 90, 17–27 (2017). https://doi.org/10.1007/s10470-016-0862-6

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  • DOI: https://doi.org/10.1007/s10470-016-0862-6

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