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A 154-μW 80-dB SNDR analog-to-digital front-end for digital hearing aids

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Abstract

A low-power, low-noise analog-to-digital front-end for digital hearing aids consisting of a preamplifier and a delta-sigma (DS) ADC with a decimation filter is presented. The high-input-impedance preamplifier has a variable gain from 14 to 23 dB. The power consumption of the preamplifier is kept low by employing operational amplifiers with class-AB output and a capacitive anti-aliasing filter. The DS modulator employs a 4th order feed-forward topology with 6-level quantization to reduce the power consumption and distortion. The designed front-end has been implemented using a 130 nm CMOS process and achieved 82.1 dB SNR and 80.1 dB SNDR over a 7.5 kHz signal band, which satisfies the requirement for digital hearing aids. The total chip dissipates a power of 154 μW from a 1.2 V supply.

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Acknowledgments

This work was supported by the R&D program of Ministry of Trade, Industry and Energy (MOTIE)/Korea evaluation institute of industrial technologies (KEIT) [10063683, Ultra-precision and ultra-low-power analog circuit IP for smart sensors of mobile devices]. The CAD tools were provided by IC Design Education Center (IDEC), Korea.

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  1. Department of Electronic Engineering, Hanyang University, Seoul, Korea

    Saemin Im & Sang-Gyu Park

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  1. Saemin Im
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  2. Sang-Gyu Park
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Correspondence to Sang-Gyu Park.

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Im, S., Park, SG. A 154-μW 80-dB SNDR analog-to-digital front-end for digital hearing aids. Analog Integr Circ Sig Process 89, 383–393 (2016). https://doi.org/10.1007/s10470-016-0850-x

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  • DOI: https://doi.org/10.1007/s10470-016-0850-x

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