Abstract
A low-jitter clock duty cycle corrector circuit applied in high performance ADC is presented in the paper, such circuits can change low accuracy input signals with different frequencies into 50% pulse width clock. The result have show that the circuit could lock duty cycle rapidly with an accuracy of 50% ± 1% in 200ns. This circuit have 10%-90% of duty cycle input, and clock jitter could be suppressed to less than 5ps. The method used in the circuit, which provides little relationship with the noise and process mismatch, is widely used Implemented in 0.18μm CMOS process.
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References
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© 2011 Springer-Verlag Berlin Heidelberg
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Huang, P., Deng, HH., Yin, YS. (2011). A High Performance 50% Clock Duty Cycle Regulator. In: Chen, R. (eds) Intelligent Computing and Information Science. ICICIS 2011. Communications in Computer and Information Science, vol 135. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-18134-4_33
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DOI: https://doi.org/10.1007/978-3-642-18134-4_33
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-18133-7
Online ISBN: 978-3-642-18134-4
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