Abstract
This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).
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Algredo-Badillo, I., Feregrino-Uribe, C., Cumplido, R. (2006). Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. In: Gavrilova, M., et al. Computational Science and Its Applications - ICCSA 2006. ICCSA 2006. Lecture Notes in Computer Science, vol 3982. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11751595_49
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DOI: https://doi.org/10.1007/11751595_49
Publisher Name: Springer, Berlin, Heidelberg
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