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Design and Tool Solutions for Monolithic Three-Dimensional Integrated Circuits

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Handbook of Computer Architecture

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Abstract

This chapter is to identify the benefits and challenges of monolithic three-dimensional integrated circuits and to introduce physical design and tool solutions to address the challenges. The physical design and tool challenges of monolithic three-dimensional integrated circuits are addressed with the following three categories: design flow, power supply integrity, and application of monolithic three-dimensional integrated circuits.

In design flow, an approach to implement monolithic three-dimensional integrated circuits is introduced. Power supply integrity issues of monolithic three-dimensional stacking technology are addressed. Lastly, deep neural network hardware using monolithic three-dimensional integrated circuits is presented as implementing low-power and high-performance deep neural network hardware is known to be difficult albeit they are widespread and powerful in recognition tasks.

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Notes

  1. 1.

    During the writeup of the manuscript, 7 nm academic PDK was not available, thus the need for our own development.

  2. 2.

    We acknowledge the contribution of ARM for their donation of a commercial 32-bir processor architecture for this research.

  3. 3.

    We used shrunk-2D design flow in this study instead of other flows that are published in the literature. This is because shrunk-2D was the only flow that supported PDN routing at the time of this manuscript. However, our results should not depend heavily on which M3D signal routing to be used in the overall flow.

References

  • Arden W, Brillouët M, Cogez P et al (2012). More-than-Moore, A White Paper. In IEEE international roadmap for devices and systems, p 31

    Google Scholar 

  • Batude P, Fenouillet-Beranger C, Pasini L et al (2015) 3DVLSI with CoolCube process: an alternative path to scaling. In Proc. symp. on VLSI technology, 2015

    Google Scholar 

  • Billoint O, Sarhan H, Rayane I et al (2015) A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool. In: Proc. design, automation and test in Europe, 2015

    Google Scholar 

  • Bozorgzadeh B, Afzali-Kusha A (2008) Decoupling capacitor optimization for nanotechnology designs. In: Proc. int. conf. on microelectronics, 2008

    Google Scholar 

  • Chang K, Acharya K, Sinha S et al Impact and design guideline of monolithic 3-D IC at the 7-nm technology node IEEE Trans VLSI System, vol. 25, p. 2118–2129, July 2017

    Google Scholar 

  • ChengY, Yu FX, Feris RS et al (2015) An exploration of parameter redundancy in deep networks with circulant projections. arXiv:1502.03436 [cs], February 2015

    Google Scholar 

  • Cheng Y, Wang D, Zhou P (2017) A survey of model compression and acceleration for deep neural networks. arXiv:1710.09282 [cs], October 2017

    Google Scholar 

  • Conneau A, Kiela D, Schwenk H et al (2017) Supervised learning of universal sentence representations from natural language inference data. arXiv:1705.02364 [cs], May 2017

    Google Scholar 

  • Courbariaux M, Bengio Y, David J-P (2015) Binary connect: training deep neural networks with binary weights during propagations. arXiv:1511.00363 [cs], November 2015

    Google Scholar 

  • Courbariaux M, Hubara I, Soudry D (2016) Binarized neural networks: training deep neural networks with weights and activations constrained to +1 or −1. arXiv:1602.02830 [cs], February 2016

    Google Scholar 

  • Das S, Whatmough P, Bull D (2015) Modeling and characterization of the system-level power delivery network for a dual-core aRM cortex-A57 cluster in 28 nm CMOS. In: Proc. int. symp. on low power electronics and design, 2015

    Google Scholar 

  • Deng L, Hinton G, Kingsbury B (2013) New types of deep neural network learning for speech recognition and related applications: an overview. In: Proc. int. conf. on acoustics, speech and signal processing, 2013

    Google Scholar 

  • Gardner WA (1984) Learning characteristics of stochastic-gradient-descent algorithms: a general study, analysis, and critique. Signal Process 6:113–133

    Article  MathSciNet  Google Scholar 

  • Garofolo JS, Lamel LF, Fisher WM et al (1993) DARPA TIMIT acoustic-phonetic continous speech corpus CD-ROM. NIST Speech Disc 1-1.1, NASA STI/Recon technical report N, vol. 93, February 1993

    Google Scholar 

  • Graves A, Mohamed A-r, Hinton G (2013) Speech recognition with deep recurrent neural networks. arXiv:1303.5778 [cs], March 2013

    Google Scholar 

  • Gray S, Radford A, Kingma DP (2017) GPU kernels for block-sparse weights

    Google Scholar 

  • Han S, Mao H, Dally WJ (2015) Deep compression: compressing deep neural networks with pruning, trained quantization and huffman coding. arXiv:1510.00149 [cs], October 2015

    Google Scholar 

  • Han S, Kang J, Mao H et al (2016) ESE: efficient speech recognition engine with sparse LSTM on FPGA. arXiv:1612.00694 [cs], December 2016

    Google Scholar 

  • He T, Fan Y, Qian Y et al (2014) Reshaping deep neural network for fast decoding by node-pruning. In: Proc. int. conf. on acoustics, speech and signal processing, 2014

    Google Scholar 

  • He K, Zhang X, Ren S et al (2015) Deep residual learning for image recognition. arXiv:1512.03385 [cs], December 2015

    Google Scholar 

  • Kadetotad D, Arunachalam S, Chakrabarti C et al (2016) Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications. In: Proc. int. conf. on computer-aided design

    Google Scholar 

  • Karpathy A, Fei-Fei L (2017) Deep visual-semantic alignments for generating image descriptions. IEEE Trans Pattern Anal Machine Intell 39:664–676

    Article  Google Scholar 

  • Khan NH, Alam SM, Hassoun S (2011) Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies. IEEE Trans VLSI System 19:647–658

    Article  Google Scholar 

  • Krizhevsky A, Sutskever I, Hinton GE (2012) ImageNet classification with deep convolutional neural networks. In: Proc. int. conf. on neural information processing systems, 2012

    Google Scholar 

  • Larsson P (1998) Resonance and damping in CMOS circuits with on-chip decoupling capacitance. IEEE Trans Circuits System 45:849–858

    Article  Google Scholar 

  • Liao W, He L, Lepak KM (2005) Temperature and supply voltage aware performance and power modeling at microarchitecture level. IEEE Trans Comput-Aided Design Integr Circuits Syst 24:1042–1053

    Article  Google Scholar 

  • Liao S, Li Z, Lin X et al (2017) Energy-efficient, high-performance, highly-compressed deep neural network design using block-circulant matrices. In: Proceedings of IEEE international conference on computer aided design

    Google Scholar 

  • Okada M, Sugaya I, Mitsuishi H et al (2014) High-precision wafer-level Cu-Cu bonding for 3DICs. In: Proc. int. electron devices meeting, 2014

    Google Scholar 

  • Pant S, Chiprout E (2006) Power grid physics and implications for CAD. In: Proc. design automation conf. 2006

    Google Scholar 

  • Panth SA, Samadi K, Du Y, Lim SK (2014) Design and CAD methodologies for low power gate-level monolithic 3D ICs. In: IEEE international symposium on low power electronics and design, 2014

    Google Scholar 

  • Povey D, Ghoshal A, Boulianne G et al (2011) The kaldi speech recognition toolkit. IEEE workshop on automatic speech recognition and understanding, January 2011

    Google Scholar 

  • Seo KI, Haran B, Gupta D et al (2014) A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI. In: Proc. symp. on VLSI technology, 2014

    Google Scholar 

  • Song T, Rim W, Jung J et al (2015) A 14 nm FinFET 128 Mb SRAM with Vrm MIN enhancement techniques for low-power applications. IEEE J Solid State Circuits 50:158–169

    Article  Google Scholar 

  • Su D, Wu X Xu L (2010) GMM-HMM acoustic model training by a two level procedure with gaussian components determined by automatic model selection. In: Proc. int. conf. on acoustics, speech and signal processing

    Google Scholar 

  • Sze V, Chen Y-H, Emer J et al (2017) Hardware for machine learning: challenges and opportunities. arXiv:1612.07625 [cs], April 2017

    Google Scholar 

  • Wu SY, Lin CY, Chiang MC et al (2013) A 16 nm FinFET CMOS technology for mobile SoC and computing applications. In: Proc. int. electron devices meeting, 2013

    Google Scholar 

  • Xiong W, Droppo J, Huang X et al (2016) The Microsoft 2016 conversational speech recognition system. arXiv:1609.03528 [cs], September 2016

    Google Scholar 

  • Yang SH, Sheu JY, Ieong MK et al (2011) 28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications. In: Proc. custom integrated circuits conf., 2011

    Google Scholar 

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Authors and Affiliations

  1. Suwon, South Korea

    Kyungwook Chang

  2. Atlanta, USA

    Sung Kyu Lim

Authors
  1. Kyungwook Chang
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  2. Sung Kyu Lim
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Correspondence to Kyungwook Chang .

Editor information

Editors and Affiliations

  1. Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

Section Editor information

  1. Computer Science and Engineering, Nanyang Technological University, Singapore, Singapore

    Mohamed M. Sabry Aly

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Chang, K., Lim, S.K. (2024). Design and Tool Solutions for Monolithic Three-Dimensional Integrated Circuits. In: Chattopadhyay, A. (eds) Handbook of Computer Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-15-6401-7_65-1

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  • DOI: https://doi.org/10.1007/978-981-15-6401-7_65-1

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-6401-7

  • Online ISBN: 978-981-15-6401-7

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