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Verification of Arithmetic and Datapath Circuits with Symbolic Simulation

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Handbook of Computer Architecture

Abstract

Symbolic simulation extends standard digital circuit simulation with symbolic representations of values, covering behaviors of a circuit for all possible instantiations of the symbolic values in a single simulation. Used as a formal verification method, symbolic simulation is algorithmically simple and intuitive, which enables precise analysis and fine-grained mitigation of computational complexity, allowing the method to handle circuits that are above the capacity of most standard formal model checking tools, as well as circuits with highly enmeshed pipelines. Symbolic simulation excels in verification of deep targeted properties of fixed-length pipelines, in particular arithmetic and other datapath circuits. It has been extensively applied in industrial verification of different kinds of integer and floating-point arithmetic circuits, such as adders, multipliers, and fused multiply-adders and dividers. Thanks to repeatable systematic verification strategies for complexity management and mitigation, such verification can be carried out routinely in development projects with rapidly evolving designs. Symbolic simulation is less optimal for verification of general consistency invariants and other inductive properties, as the method does not automate reachable-state analysis and requires a higher degree of human interaction and expertise than standard model checking tools.

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Acknowledgements

This chapter summarizes almost three decades of work. At the time of its writing, more than 60 people have directly contributed to Intel’s shared arithmetic verification code-base on over 50 design projects. A much higher number have contributed intellectually to the endeavor, both inside Intel and at large. It has been a team effort. We would like to express our sincere thanks to each and every member of the team.

We would also like to thank Intel’s design and validation management over the years for trusting and encouraging this work. There are more names than we can mention; however, we would like to express our special thanks to Bob Bentley and Alon Flaisher for their crucial long-term support.

Finally, we would like to thank Jesse Bingham, Levent Erkok, Robert Jones, Joe Leslie-Hurd, Sayak Ray, and Annette Upton for their detailed feedback on the drafts of this text.

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Authors and Affiliations

  1. Core and Client Development Group, Intel Corporation, Hillsboro, OR, USA

    Roope Kaivola & John O’Leary

Authors
  1. Roope Kaivola
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  2. John O’Leary
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Correspondence to Roope Kaivola or John O’Leary .

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Editors and Affiliations

  1. Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

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  1. Intel, 6250 Santa Teresa Blvd., Apt 121, 95119, San Jose, California, USA

    Ray Sayak

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Kaivola, R., O’Leary, J. (2022). Verification of Arithmetic and Datapath Circuits with Symbolic Simulation. In: Chattopadhyay, A. (eds) Handbook of Computer Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-15-6401-7_37-1

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  • DOI: https://doi.org/10.1007/978-981-15-6401-7_37-1

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