Skip to main content

Fault Tolerant Architectures

  • Living reference work entry
  • First Online:
Handbook of Computer Architecture

Abstract

Fault-tolerant computing has been the cornerstone of reliable computing using electronic systems. Traditionally, fault-tolerant system design has been primarily driven by the system’s operating environment and the resulting fault scenarios due to external disturbances. However, with the growing unreliability of modern semiconductor technologies, reliable computing requires designing fault tolerance across multiple layers of the system stack. Further, the growing impact of intrinsic fault mechanisms such as aging requires designing fault-tolerant architectures across application domains. To this end, emerging technologies, both semiconductor devices and applications, have brought about novel challenges to designing fault-tolerant architectures.

This chapter provides a brief overview of the landscape of fault-tolerant architectures, from the fundamentals to the state-of-the-art and open research areas. The chapter begins with the background of faults, errors, and reliability estimations. Fault-tolerant architecture for computation, memory/storage, and communication are briefly covered. Related state-of-the-art topics such as cross-layer reliability and fault-tolerance for emerging devices (NVMs) and emerging applications (AI/ML) are also covered in the chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

References

  • Adday GH, Subramaniam SK, Zukarnain ZA, Samian N (2022) Fault tolerance structures in wireless sensor networks (wsns): survey, classification, and future directions. Sensors 22(16). https://doi.org/10.3390/s22166041, https://www.mdpi.com/1424-8220/22/16/6041

  • Austin TM (1999) Diva: a reliable substrate for deep submicron microarchitecture design. In: MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, pp 196–207. https://doi.org/10.1109/MICRO.1999.809458

  • Avizienis A, Laprie J, Randell B, Landwehr C (2004) Basic concepts and taxonomy of dependable and secure computing. IEEE Trans Depend Secure Comput 1(1):11–33. https://doi.org/10.1109/TDSC.2004.2

    Article  Google Scholar 

  • Arzt E, Kraft O, Sanchez JE, Bader S, Nix WD (1992) Electromigration resistance and mechanical strength

    Google Scholar 

  • Balaji A, Wu Y, Das A, Catthoor F, Schaafsma S (2019) Exploration of segmented bus as scalable global interconnect for neuromorphic computing. In: GLSVLSI

    Google Scholar 

  • Bar-El H, Choukri H, Naccache D, Tunstall M, Whelan C (2006) The sorcerer’s apprentice guide to fault attacks. Proc IEEE 94(2):370–382. https://doi.org/10.1109/JPROC.2005.862424

    Article  Google Scholar 

  • Baraza J, Gracia J, Gil D, Gil P (2002) A prototype of a vhdl-based fault injection tool: description and application. J. Syst. Architect 47(10):847–867. https://doi.org/https://doi.org/10.1016/S1383-7621(01)00036-4, https://www.sciencedirect.com/science/article/pii/S1383762101000364

  • Biasielli M, Bolchini C, Cassano L, Mazzeo A, Miele A (2022) Approximation-based fault tolerance in image processing applications. IEEE Trans Emerg Top Comput 10(2):648–661. https://doi.org/10.1109/TETC.2021.3100623

    Google Scholar 

  • Binder D, Smith EC, Holman AB (1975) Satellite anomalies from galactic cosmic rays. IEEE Trans Nucl Sci 22(6):2675–2680. https://doi.org/10.1109/TNS.1975.4328188

    Article  Google Scholar 

  • Blaauw D, Kalaiselvan S, Lai K, Ma W, Pant S, Tokunaga C, Das S, Bull D (2008) Razor II: in situ error detection and correction for PVT and SER tolerance. In: 2008 IEEE International Solid-State Circuits Conference – Digest of Technical Papers, pp 400–622. https://doi.org/10.1109/ISSCC.2008.4523226

  • Carter NP, Naeimi H, Gardner DS (2010) Design techniques for cross-layer resilience. In: 2010 Design, Automation Test in Europe Conference Exhibition (DATE 2010), pp 1023–1028. https://doi.org/10.1109/DATE.2010.5456960

  • Chen PM, Lee EK, Gibson GA, Katz RH, Patterson DA (1994) Raid: high-performance, reliable secondary storage. ACM Comput Surv 26(2):145–185. https://doi.org/10.1145/176979.176981

    Article  Google Scholar 

  • Cheng E, Mirkhani S, Szafaryn LG, Cher CY, Cho H, Skadron K, Stan MR, Lilja K, Abraham JA, Bose P, Mitra S (2016) Clear: cross-layer exploration for architecting resilience – combining hardware and software techniques to tolerate soft errors in processor cores. In: Proceedings of the 53rd Annual Design Automation Conference, DAC’16. ACM, New York, pp 68:1–68:6. https://doi.org/10.1145/2897937.2897996, http://doi.acm.org/10.1145/2897937.2897996

  • Cho H, Cheng E, Shepherd T, Cher CY, Mitra S (2017) System-level effects of soft errors in uncore components. IEEE Trans Comput-Aided Design Integr Circuits Syst 36(9):1497–1510. https://doi.org/10.1109/TCAD.2017.2651824

    Article  Google Scholar 

  • Cüppers F, Menzel S, Bengel C, Hardtdegen A, Von Witzleben M, Böttger U, Waser R, Hoffmann-Eifert S (2019) Exploiting the switching dynamics of HfO2-based ReRAM devices for reliable analog memristive behavior. APL Mater 7(9):091105. https://doi.org/10.1063/1.5108654

    Article  Google Scholar 

  • Das A, Kumar A, Veeravalli B (2013) Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems. In: 2013 Design, Automation Test in Europe Conference Exhibition (DATE), pp 689–694. https://doi.org/10.7873/DATE.2013.149

  • Dubrova E (2013) Introduction. Springer, New York, pp 1–4. https://doi.org/10.1007/978-1-4614-2113-9_1

    Google Scholar 

  • Dumitriu V, Kirischian L, Kirischian V (2016) Run-time recovery mechanism for transient and permanent hardware faults based on distributed, self-organized dynamic partially reconfigurable systems. IEEE Trans Comput 65(9):2835–2847. https://doi.org/10.1109/TC.2015.2506558

    Article  MathSciNet  MATH  Google Scholar 

  • Effah E, Thiare O (2018) Survey: faults, fault detection and fault tolerance techniques in wireless sensor networks. Int J Comput Sci Inf Secur(IJCSIS) 16(10):1–14

    Google Scholar 

  • Hamming RW (1950) Error detecting and error correcting codes. Bell Syst Tech J 29(2):147–160. https://doi.org/10.1002/j.1538-7305.1950.tb00463.x

    Article  MathSciNet  MATH  Google Scholar 

  • Henkel J, Bauer L, Zhang H, Rehman S, Shafique M (2014) Multi-layer dependability: From microarchitecture to application level. In: Proceedings of the 51st Annual Design Automation Conference. Association for Computing Machinery, New York, p 1–6. https://doi.org/10.1145/2593069.2596683

    Google Scholar 

  • Hsiao MY (1970) A class of optimal minimum odd-weight-column sec-ded codes. IBM J Res Develop 14(4):395–401. https://doi.org/10.1147/rd.144.0395

    Article  Google Scholar 

  • Isik M, Paul A, Varshika ML, Das A (2022) A design methodology for fault-tolerant computing using astrocyte neural networks. In: Proceedings of the 19th ACM International Conference on Computing Frontiers, pp 169–172

    Google Scholar 

  • Kakoee MR, Bertacco V, Benini L (2011) Relinoc: a reliable network for priority-based on-chip communication. In: 2011 Design, Automation Test in Europe, pp 1–6. https://doi.org/10.1109/DATE.2011.5763112

  • Karaklajić D, Schmidt JM, Verbauwhede I (2013) Hardware designer’s guide to fault attacks. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(12):2295–2306. https://doi.org/10.1109/TVLSI.2012.2231707

    Article  Google Scholar 

  • Kim J, Sullivan M, Erez M (2015) Bamboo ECC: strong, safe, and flexible codes for reliable computer memory. In: 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp 101–112. https://doi.org/10.1109/HPCA.2015.7056025

  • Kim BS, Choi J, Min SL (2019) Design tradeoffs for ssd reliability. In: Proceedings of the 17th USENIX Conference on File and Storage Technologies, FAST’19. USENIX Association, USA, pp 281–294

    Google Scholar 

  • Koch D, Haubelt C, Teich J (2007) Efficient hardware checkpointing: concepts, overhead analysis, and implementation. In: Proceedings of the 2007 ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA’07. ACM, New York, pp 188–196. https://doi.org/10.1145/1216919.1216950, http://doi.acm.org/10.1145/1216919.1216950

  • Kraak D, Taouil M, Agbo I, Hamdioui S, Weckx P, Cosemans S, Catthoor F (2019) Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. TVLSI. https://doi.org/10.1109/TVLSI.2019.2902881

  • Kriebel F, Rehman S, Sun D, Shafique M, Henkel J (2014) Aser: adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. In: 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), pp 1–6. https://doi.org/10.1145/2593069.2593094

  • Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP (2008) Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. ACM Trans Des Autom Electron Syst 13(1). https://doi.org/10.1145/1297666.1297674

  • Latifi S, Zamirai B, Mahlke S (2020) PolygraphMR: enhancing the reliability and dependability of CNNs. In: DSN

    Google Scholar 

  • Liu C, Hu M, Strachan JP, Li H (2017) Rescuing memristor-based neuromorphic design with high defects. In: DAC

    Google Scholar 

  • Mallik A, Garbin D, Fantini A, Rodopoulos D, Degraeve R, Stuijt J, Das A, Schaafsma S, Debacker P, Donadio G et al (2017) Design-technology co-optimization for OxRRAM-based synaptic processing unit. In: VLSIT

    Google Scholar 

  • Mead C (1990) Neuromorphic electronic systems. Proc IEEE, vol. 78(10), pp. 1629–1636. https://doi.org/10.1109/5.58356

    Article  Google Scholar 

  • Mohanram K, Touba NA (2003) Cost-effective approach for reducing soft error failure rate in logic circuits. In: International Test Conference, 2003. Proceedings, vol 1, ITC 2003, pp 893–901. https://doi.org/10.1109/TEST.2003.1271075

  • Moore GE (2006) Cramming more components onto integrated circuits, reprinted from electronics, vol 38, number 8, 19 Apr, 1965, pp.114 ff. IEEE Solid-State Circuits Soc Newslett 11(3):33–35. https://doi.org/10.1109/N-SSC.2006.4785860

  • Morikawa T, Kurotsuchi K, Kinoshita M, Matsuzaki N, Matsui Y, Fujisaki Y, Hanzawa S, Kotabe A, Terao M, Moriya H, et al. (2007) Doped In-Ge-Te phase change memory featuring stable operation and good data retention. In: IEDM

    Google Scholar 

  • Mukherjee SS, Kontz M, Reinhardt SK (2002) Detailed design and evaluation of redundant multi-threading alternatives. In: Proceedings 29th Annual International Symposium on Computer Architecture, pp 99–110. https://doi.org/10.1109/ISCA.2002.1003566

  • Mukherjee SS, Weaver C, Emer J, Reinhardt SK, Austin T (2003) A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In: Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36, pp 29–40. https://doi.org/10.1109/MICRO.2003.1253181

  • Mulaosmanovic H, Ocker J, Müller S, Noack M, Müller J, Polakowski P, Mikolajick T, Slesazeck S (2017) Novel ferroelectric FET based synapse for neuromorphic systems. In: VLSIT

    Google Scholar 

  • Mutlu O (2013) Memory scaling: a systems architecture perspective. In: IMW

    Google Scholar 

  • Nandakumar SR, Le Gallo M, Boybat I, Rajendran B, Sebastian A, Eleftheriou E (2018) A phase-change memory model for neuromorphic computing. JAP 124(15): 152135. https://doi.org/10.1063/1.5042408

    Google Scholar 

  • Park S, Li S, Zhang Z, Mahlke S (2020) Low-cost prediction-based fault protection strategy. In: CGO

    Google Scholar 

  • Parpura V, Basarsky TA, Liu F, Jeftinija K, Jeftinija S, Haydon PG (1994) Glutamate-mediated astrocyte–neuron signalling. Nature 369(6483), 744–747. https://doi.org/10.1038/369744a0

    Article  Google Scholar 

  • Patterson DA, Gibson G, Katz RH (1988) A case for redundant arrays of inexpensive disks (raid). SIGMOD Rec 17(3):109–116. https://doi.org/10.1145/971701.50214

    Article  Google Scholar 

  • Postman J, Chiang P (2012) A survey addressing on-chip interconnect: energy and reliability considerations. ISRN Electronics 2012

    Google Scholar 

  • Rambo EA, Kadeed T, Ernst R, Seo M, Kurdahi F, Donyanavard B, de Melo CB, Maity B, Moazzemi K, Stewart K, Yi S, Rahmani AM, Dutt N, Maurer F, Vu Doan NA, Surhonne A, Wild T, Herkersdorf A (2019) The information processing factory: A paradigm for life cycle management of dependable systems. In: 2019 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp 1–10. https://doi.org/10.1145/3349567.3357391

  • Rao TRN (1974) Error Coding for Arithmetic Processors. Academic Press, Inc., Orlando

    MATH  Google Scholar 

  • Rao RR, Blaauw D, Sylvester D (2006) Soft error reduction in combinational logic using gate resizing and flipflop selection. In: 2006 IEEE/ACM International Conference on Computer Aided Design, pp 502–509. https://doi.org/10.1109/ICCAD.2006.320165

  • Reagen B, Gupta U, Pentecost L, Whatmough P, Lee SK, Mulholland N, Brooks D, Wei GY (2018) Ares: a framework for quantifying the resilience of deep neural networks. In: DAC

    Google Scholar 

  • Reed I, Solomon G (1960) Polynomial codes over certain finite fields. J Soc Ind Appl Math 8(2):300–304. https://doi.org/10.1137/0108018

    Article  MathSciNet  MATH  Google Scholar 

  • Rehman S, Chen K, Kriebel F, Toma A, Shafique M, Chen J, Henkel J (2016) Cross-layer software dependability on unreliable hardware. IEEE Trans Comput 65(1):80–94. https://doi.org/10.1109/TC.2015.2417554

    Article  MathSciNet  MATH  Google Scholar 

  • Sahoo SS (2019) A cross-layer reliability-integrated system-level design methodology for heterogeneous multiprocessor SoC-based embedded systems. PhD thesis, National University of Singapore (Singapore)

    Google Scholar 

  • Sahoo SS, Veeravalli B, Kumar A (2016) Cross-layer fault-tolerant design of real-time systems. In: DFTS, pp 63–68. https://doi.org/10.1109/DFT.2016.7684071

  • Sahoo SS, Nguyen TDA, Veeravalli B, Kumar A (2018a) Lifetime-aware design methodology for dynamic partially reconfigurable systems. In: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp 393–398. https://doi.org/10.1109/ASPDAC.2018.8297355

  • Sahoo SS, Veeravalli B, Kumar A (2018b) CLRFrame: an analysis framework for designing cross-layer reliability in embedded systems. In: 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, 6–10 Jan, 2018, pp 307–312. https://doi.org/10.1109/VLSID.2018.81, http://doi.ieeecomputersociety.org/10.1109/VLSID.2018.81

  • Sahoo S, Nguyen T, Veeravalli B, Kumar A (2019) Multi-objective design space exploration for system partitioning of fpga-based dynamic partially reconfigurable systems. Integration 67:95–107. https://doi.org/10.1016/j.vlsi.2018.10.006

    Article  Google Scholar 

  • Sahoo SS, Veeravalli B, Kumar A (2020a) CL(R)Early: an Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems. In: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp 1–6. https://doi.org/10.1109/DAC18072.2020.9218747

  • Sahoo SS, Veeravalli B, Kumar A (2020b) Markov chain-based modeling and analysis of checkpointing with rollback recovery for efficient dse in soft real-time systems. In: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp 1–6. https://doi.org/10.1109/DFT50435.2020.9250892

  • Santini T, Rech P, Sartor A, Corrêa UB, Carro L, Wagner F (2015) Evaluation of failures masking across the software stack. MEDIAN

    Google Scholar 

  • Santos R, Venkataraman S, Kumar A (2017) Scrubbing mechanism for heterogeneous applications in reconfigurable devices. ACM Trans Des Autom Electron Syst 22(2). https://doi.org/10.1145/2997646

  • Schmidt AG, French M (2013) Fast lossless image compression with radiation hardening by hardware/software co-design on platform fpgas. In: 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, pp 103–106. https://doi.org/10.1109/ASAP.2013.6567560

  • Secco J, Corinto F, Sebastian A (2017) Flux–charge memristor model for phase change memory. TCAS II: Express Briefs

    Google Scholar 

  • Shafique M, Rehman S, Aceituno PV, Henkel J (2013) Exploiting program-level masking and error propagation for constrained reliability optimization. In: 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pp 1–9. https://doi.org/10.1145/2463209.2488755

  • Shim B, Shanbhag N (2006) Energy-efficient soft error-tolerant digital signal processing. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(4):336–348. https://doi.org/10.1109/TVLSI.2006.874359

    Article  Google Scholar 

  • Shim B, Sridhara S, Shanbhag N (2004) Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans Very Large Scale Integr (VLSI) Syst 12(5):497–510. https://doi.org/10.1109/TVLSI.2004.826201

    Article  Google Scholar 

  • Shim W, Luo Y, Seo Js, Yu S (2020) Impact of read disturb on multilevel RRAM based inference engine: experiments and model prediction. In: IRPS

    Google Scholar 

  • Shubu M (2008) Architecture design for soft errors. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA

    Google Scholar 

  • Siddique A, Basu K, Hoque KA (2021) Exploring fault-energy trade-offs in approximate DNN hardware accelerators. In: ISQED

    Google Scholar 

  • Slayman CW (2005) Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations. IEEE Trans Device Mater Reliab 5(3):397–404. https://doi.org/10.1109/TDMR.2005.856487

    Article  Google Scholar 

  • Slegel TJ, Averill RM, Check MA, Giamei BC, Krumm BW, Krygowski CA, Li WH, Liptay JS, MacDougall JD, McPherson TJ, Navarro JA, Schwarz EM, Shum K, Webb CF (1999) Ibm’s S/390 G5 microprocessor design. IEEE Micro 19(2):12–23. https://doi.org/10.1109/40.755464

    Article  Google Scholar 

  • Sorin DJ (2009) Fault tolerant computer architecture. Syn Lectures Comput Architect 4(1):1–104

    Article  Google Scholar 

  • Srinivasan S, Krishnan R, Mangalagiri P, Xie Y, Narayanan V, Irwin MJ, Sarpatwari K (2008) Toward increasing fpga lifetime. IEEE Trans Depend Secure Comput 5(2):115–127. https://doi.org/10.1109/TDSC.2007.70235

    Article  Google Scholar 

  • Titirsha T, Song S, Das A, Krichmar J, Dutt N, Kandasamy N, Catthoor F (2022) Endurance-aware mapping of spiking neural networks to neuromorphic hardware. TPDS 33(2):288–301. https://doi.org/10.1109/TPDS.2021.3065591

    Google Scholar 

  • Varshika ML, Corradi F, Das A (2022) Nonvolatile memories in spiking neural network architectures: current and emerging trends. Electronics 11(10):1610. https://doi.org/10.3390/electronics11101610

    Article  Google Scholar 

  • Vihman L, Kruusmaa M, Raik J (2020) Data-driven cross-layer fault management architecture for sensor networks. In: 2020 16th European Dependable Computing Conference (EDCC), pp 33–40. https://doi.org/10.1109/EDCC51268.2020.00015

  • Vincent AF, Larroque J, Locatelli N, Romdhane NB, Bichler O, Gamrat C, Zhao WS, Klein JO, Galdin-Retailleau S, Querlioz D (2015) Spin-transfer torque magnetic memory as a stochastic memristive synapse for neuromorphic systems. TBCAS 9(2):166–174. https://doi.org/10.1109/TBCAS.2015.2414423

    Google Scholar 

  • Wang Z, Chattopadhyay A (2017) High-level Estimation and Exploration of Reliability for Multi-processor System-on-chip. Springer. https://link.springer.com/book/10.1007/978-981-10-1073-6

    Google Scholar 

  • Wang Z, Li R, Chattopadhyay A (2013) Opportunistic redundancy for improving reliability of embedded processors. In: 2013 8th IEEE Design and Test Symposium, pp 1–6. https://doi.org/10.1109/IDT.2013.6727090

  • Wang Z, Paul G, Chattopadhyay A (2014) Processor design with asymmetric reliability. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp 565–570. https://doi.org/10.1109/ISVLSI.2014.63

  • Wang Z, Karakonstantis G, Chattopadhyay A (2016) A low overhead error confinement method based on application statistical characteristics. In: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1168–1171

    Google Scholar 

  • Wirthlin MJ, Keller AM, McCloskey C, Ridd P, Lee D, Draper J (2016) SEU mitigation and validation of the LEON3 soft processor using triple modular redundancy for space processing. In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA ’16. ACM, New York, pp 205–214. https://doi.org/10.1145/2847263.2847278, http://doi.acm.org/10.1145/2847263.2847278

  • Wulf WA, McKee SA (1995) Hitting the memory wall: implications of the obvious. SIGARCH Comput. Archit. News 23(1):20–24. https://doi.org/10.1145/216585.216588

    Article  Google Scholar 

  • Xiang Y, Chantem T, Dick RP, Hu XS, Shang L (2010) System-level reliability modeling for mpsocs. In: 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp 297–306

    Google Scholar 

  • Yoon DH, Erez M (2010) Virtualized and flexible ecc for main memory. In: Proceedings of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, ASPLOS XV. ACM, New York, pp 397–408. https://doi.org/10.1145/1736020.1736064, http://doi.acm.org/10.1145/1736020.1736064

  • Yuan G, Liao Z, Ma X, Cai Y, Kong Z, Shen X, Fu J, Li Z, Zhang C, Peng H, et al. (2021) Improving DNN fault tolerance using weight pruning and differential crossbar mapping for ReRAM-based edge AI. In: ISQED

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Akash Kumar .

Editor information

Editors and Affiliations

Section Editor information

Rights and permissions

Reprints and permissions

Copyright information

© 2023 Springer Nature Singapore Pte Ltd.

About this entry

Check for updates. Verify currency and authenticity via CrossMark

Cite this entry

Sahoo, S.S., Das, A., Kumar, A. (2023). Fault Tolerant Architectures. In: Chattopadhyay, A. (eds) Handbook of Computer Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-15-6401-7_11-1

Download citation

  • DOI: https://doi.org/10.1007/978-981-15-6401-7_11-1

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-6401-7

  • Online ISBN: 978-981-15-6401-7

  • eBook Packages: Springer Reference EngineeringReference Module Computer Science and Engineering

Publish with us

Policies and ethics