Abstract
The use of heterogeneous Multi-Processor System-on-Chip (MPSoC) is a widely accepted solution to address the increasing demands on high performance and energy efficiency for modern embedded devices. To enable the full potential of these platforms, new tools are needed to tackle the programming complexity of MPSoCs, while allowing for high productivity. This chapter discusses the MPSoC Application Programming Studio (MAPS), a framework that provides facilities for expressing parallelism and tool flows for parallelization, mapping/scheduling, and code generation for heterogeneous MPSoCs. Two case studies of the use of MAPS in commercial environments are presented. This chapter closes by discussing early experiences of transferring the MAPS technology into Silexica GmbH, a start-up company that provides multi-core programming tools.
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References
Aguilar M, Jimenez R, Leupers R, Ascheid G (2014) Improving performance and productivity for software development on TI multicore DSP platforms. In: 6th European embedded design in education and research conference (EDERC), 2014, pp 31–35
Aguilar MA, Eusse JF, Leupers R, Ascheid G, Odendahl M (2015) Extraction of kahn process networks from while loops in embedded software. In: 12th IEEE international conference on embedded software and systems (ICESS)
Aguilar MA, Eusse JF, Ray P, Leupers R, Ascheid G, Sheng W, Sharma P (2015) Parallelism extraction in embedded software for Android devices. In: Proceedings of the XV international conference on embedded computer systems: architectures, modeling and simulation, SAMOS XV
Aho AV, Lam MS, Sethi R, Ullman JD (2006) Compilers: principles, techniques, and tools, 2nd edn. Prentice Hall, Boston
Basten T, Hoogerbrugge J (2001) Efficient execution of process networks. In: Chalmers A, Mirmehdi M, Muller H (eds) Communicating process architectures – 2001. IOS Press, Amsterdam, pp 1–14
Brunet SC (2015) Analysis and optimization of dynamic dataflow programs. Ph.D. thesis, Ecole Polytechnique Federale de Lausanne (EPFL)
C6678: Multicore fixed and floating-point digital signal processor. http://www.ti.com/product/TMS320C6678/technicaldocuments
Castrillon J, Leupers R (2014) Programming heterogeneous MPSoCs: tool flows to close the software productivity gap. Springer, Cham
Castrillon J, Leupers R, Ascheid G (2013) MAPS: mapping concurrent dataflow applications to heterogeneous MPSoCs. IEEE Trans Ind Inf 9(1):527–545
Castrillon J, Tretter A, Leupers R, Ascheid G (2012) Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. In: Proceedings of the 49th annual design automation conference, DAC’12. ACM, New York, pp 1266–1271
Castrillon J, Velasquez R, Stulova A, Sheng W, Ceng J, Leupers R, Ascheid G, Meyr H (2010) Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. In: Proceedings of the conference on design, automation and test in Europe, DATE’10. European design and automation association, pp 753–758
Ceng J, Castrillon J, Sheng W, Scharwächter H, Leupers R, Ascheid G, Meyr H, Isshiki T, Kunieda H (2008) MAPS: an integrated framework for MPSoC application parallelization. In: Proceedings of the 45th annual design automation conference. ACM, pp 754–759
Cheung E, Hsieh H, Balarin F (2007) Automatic Buffer Sizing for Rate-constrained KPN applications on multiprocessor System-on-Chip. In: Proceedings of the 2007 IEEE international high level design validation and test workshop. IEEE, pp 37–44
Das A, Singh AK, Kumar A (2015) Execution trace–driven energy-reliability optimization for multimedia MPSoCs. ACM Trans Reconfigurable Technol Syst 8(3):18:1–18:19
Eusse JF, Williams C, Leupers R (2015) CoEx: a novel profiling-based algorithm/architecture co-exploration for ASIP design. ACM Trans Reconfigurable Technol Syst 8(3):17:1–17:16
Eusse J, Williams C, Murillo L, Leupers R, Ascheid G (2014) Pre-architectural performance estimation for ASIP design based on abstract processor models. In: International conference on embedded computer systems: architectures, modeling, and simulation (SAMOS XIV), 2014, pp 133–140
Geilen M, Basten T (2003) Requirements on the execution of kahn process networks. In: Proceedings of the 12th European symposium on programming, ESOP 2003. Springer, pp 319–334
Goens A, Castrillon J (2015) Analysis of process traces for mapping dynamic kpn applications to mpsocs. In: Proceedings of the IFIP international embedded systems symposium (IESS), Foz do Iguaçu
International Data Corporation (IDC) (2015) IDC: smartphone OS market share, 2015 Q2. http://www.idc.com/prodserv/smartphone-os-market-share.jsp
Johnson R, Pingali K (1993) Dependence-based program analysis. In: Proceedings of the ACM SIGPLAN 1993 conference on programming language design and implementation, PLDI’93. ACM, New York, pp 78–89. DOI 10.1145/155090.155098
Kahn G (1974) The semantics of a simple language for parallel programming. In: IFIP congress, pp 471–475
Kennedy K, Allen JR (2002) Optimizing compilers for modern architectures: a dependence-based approach. Morgan Kaufmann Publishers Inc., San Francisco
Kwok YK, Ahmad I (1999) Static scheduling algorithms for allocating directed task graphs to multiprocessors. ACM Comput Surv 31(4):406–471. DOI 10.1145/344588.344618
Lattner C (2008) LLVM and clang: next generation compiler technology. In: The BSD conference, Ottawa
Lee EA, Messerschmitt DG (1987) Synchronous data flow. Proc IEEE 75(9):1235–1245
Moreira O, Valente F, Bekooij M (2007) Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor. In: EMSOFT’07: Proceedings of the 7th ACM & IEEE international conference on embedded software. ACM, pp 57–66
Nexus 7 (2013) http://www.asus.com/Tablets_Mobile/Nexus_7_2013/
Parks TM (1995) Bounded scheduling of process networks. Ph.D. thesis, EECS Department, University of California, Berkeley
Pimentel A, Erbas C, Polstra S (2006) A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans Comput 55(2):99–112
Stuijk S, Basten T, Geilen MCW, Corporaal H (2007) Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs. In: DAC’07: Proceedings of the 44th annual design automation conference. ACM, New York, pp 777–782
Thiele L, Bacivarov I, Haid W, Huang K (2007) Mapping applications to tiled multiprocessor embedded systems. In: International conference on application of concurrency to system design, pp 29–40. DOI 10.1109/ ACSD.2007.53
Thies W, Chandrasekhar V, Amarasinghe S (2007) A practical approach to exploiting coarse-grained pipeline parallelism in C programs. In: Proceedings of the 40th annual IEEE/ACM international symposium on microarchitecture, MICRO 40. IEEE, pp 356–369
Thies W, Karczmarek M, Amarasinghe S (2002) StreamIt: a language for streaming applications. In: International conference on compiler construction, Grenoble
Tournavitis G (2011) Profile-driven parallelization of sequential programs. Ph.D. thesis, University of Edinburgh
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Leupers, R., Aguilar, M., Eusse, J.F., Castrillon, J., Sheng, W. (2016). MAPS: A Software Development Environment for Embedded Multi-core Applications. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7358-4_2-1
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DOI: https://doi.org/10.1007/978-94-017-7358-4_2-1
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