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Handbook of Hardware/Software Codesign pp 867–913Cite as

Microarchitecture-Level SoC Design

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Abstract

In this chapter we consider the issues related to integrating microarchitectural IP blocks into complex SoCs while satisfying performance, power, thermal, and reliability constraints. We first review different abstraction levels for SoC design that promote IP reuse, and which enable fast simulation for early functional validation of the SoC platform. Since SoCs must satisfy a multitude of interrelated constraints, we then present high-level power, thermal, and reliability models for predicting these constraints. These constraints are not unrelated and their interactions must be considered, modeled and evaluated. Once constraints are modeled, we must explore the design space trading off performance, power and reliability. Several case studies are presented illustrating how the design space can be explored across layers, and what modifications could be applied at design time and/or runtime to deal with reliability issues that may arise.

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  • DOI: 10.1007/978-94-017-7267-9_28
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Abbreviations

AHB:

Advanced High-performance Bus

APB:

Advanced Peripheral Bus

ASIC:

Application-Specific Integrated Circuit

BER:

Bit Error Rate

BLB:

Bit Lock Block

CA:

Cycle Accurate

CDMA:

Code Division Multiple Access

CMOS:

Complementary Metal-Oxide-Semiconductor

CMP:

Chip Multi-Processor

CPU:

Central Processing Unit

DFS:

Dynamic Frequency Scaling

DMA:

Direct Memory Access

DTA:

Dynamic Timing Analysis

DTM:

Dynamic Thermal Management

DVFS:

Dynamic Voltage and Frequency Scaling

DVS:

Dynamic Voltage Scaling

ESL:

Electronic System Level

GPIO:

General-Purpose Input/Output-pin

IDC:

Inquisitive Defect Cache

IP:

Intellectual Property

IPB:

Intellectual Property Block

ISS:

Instruction-Set Simulator

ITRS:

International Technology Roadmap for Semiconductors

MOSFET:

Metal-Oxide-Semiconductor Field-Effect Transistor

MPSoC:

Multi-Processor System-on-Chip

MTF:

Mean Time to Failure

NMOS:

Negative-type Metal-Oxide-Semiconductor

PDF:

Probability Density Function

PI:

Principal Investigator

PMOS:

Positive-type Metal-Oxide-Semiconductor

PSNR:

Peak SNR

RAM:

Random-Access Memory

RDF:

Random Dopant Fluctuations

ROM:

Read-Only Memory

RTL:

Register Transfer Level

SNR:

Signal-to-Noise Ratio

SoC:

System-on-Chip

SRAM:

Static Random-Access Memory

SSTA:

Statistical Static Timing Analysis

T-BCA:

Transaction-based Bus Cycle Accurate

TLM:

Transaction-Level Model

VFI:

Voltage/Frequency Island

VOS:

Voltage Over Scaling

WCDMA:

Wideband CDMA

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Author information

Authors and Affiliations

  1. Digital Media and Communications R&D Center, Samsung Electronics, Seoul, Korea

    Young-Hwan Park

  2. Broadcom Corp., San Jose, CA, USA

    Amin Khajeh

  3. Center for Embedded and Cyber-Physical Systems, University of California Irvine, 92697, Irvine, CA, USA

    Jun Yong Shin, Fadi Kurdahi, Ahmed Eltawil & Nikil Dutt

Authors
  1. Young-Hwan Park
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  2. Amin Khajeh
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  3. Jun Yong Shin
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  4. Fadi Kurdahi
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  5. Ahmed Eltawil
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  6. Nikil Dutt
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Corresponding author

Correspondence to Fadi Kurdahi .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Prof. Dr. Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Prof. Dr. Jürgen Teich

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Park, YH., Khajeh, A., Shin, J.Y., Kurdahi, F., Eltawil, A., Dutt, N. (2017). Microarchitecture-Level SoC Design. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_28

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