Skip to main content
SpringerLink
Log in
Book cover

Handbook of Hardware/Software Codesign pp 867–913Cite as

Microarchitecture-Level SoC Design

  • Reference work entry
  • First Online:

  • 3462 Accesses

Abstract

In this chapter we consider the issues related to integrating microarchitectural IP blocks into complex SoCs while satisfying performance, power, thermal, and reliability constraints. We first review different abstraction levels for SoC design that promote IP reuse, and which enable fast simulation for early functional validation of the SoC platform. Since SoCs must satisfy a multitude of interrelated constraints, we then present high-level power, thermal, and reliability models for predicting these constraints. These constraints are not unrelated and their interactions must be considered, modeled and evaluated. Once constraints are modeled, we must explore the design space trading off performance, power and reliability. Several case studies are presented illustrating how the design space can be explored across layers, and what modifications could be applied at design time and/or runtime to deal with reliability issues that may arise.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   699.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD   949.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Abbreviations

AHB:

Advanced High-performance Bus

APB:

Advanced Peripheral Bus

ASIC:

Application-Specific Integrated Circuit

BER:

Bit Error Rate

BLB:

Bit Lock Block

CA:

Cycle Accurate

CDMA:

Code Division Multiple Access

CMOS:

Complementary Metal-Oxide-Semiconductor

CMP:

Chip Multi-Processor

CPU:

Central Processing Unit

DFS:

Dynamic Frequency Scaling

DMA:

Direct Memory Access

DTA:

Dynamic Timing Analysis

DTM:

Dynamic Thermal Management

DVFS:

Dynamic Voltage and Frequency Scaling

DVS:

Dynamic Voltage Scaling

ESL:

Electronic System Level

GPIO:

General-Purpose Input/Output-pin

IDC:

Inquisitive Defect Cache

IP:

Intellectual Property

IPB:

Intellectual Property Block

ISS:

Instruction-Set Simulator

ITRS:

International Technology Roadmap for Semiconductors

MOSFET:

Metal-Oxide-Semiconductor Field-Effect Transistor

MPSoC:

Multi-Processor System-on-Chip

MTF:

Mean Time to Failure

NMOS:

Negative-type Metal-Oxide-Semiconductor

PDF:

Probability Density Function

PI:

Principal Investigator

PMOS:

Positive-type Metal-Oxide-Semiconductor

PSNR:

Peak SNR

RAM:

Random-Access Memory

RDF:

Random Dopant Fluctuations

ROM:

Read-Only Memory

RTL:

Register Transfer Level

SNR:

Signal-to-Noise Ratio

SoC:

System-on-Chip

SRAM:

Static Random-Access Memory

SSTA:

Statistical Static Timing Analysis

T-BCA:

Transaction-based Bus Cycle Accurate

TLM:

Transaction-Level Model

VFI:

Voltage/Frequency Island

VOS:

Voltage Over Scaling

WCDMA:

Wideband CDMA

References

  1. Predictive technology model(ptm). http://www.eas.asu.edu

  2. Synopsys design compiler, primetime px, power compiler. http://www.synopsys.com

  3. Standard performance evaluation council, performance evaluation in the new millennium, v.1.1 (2000)

    Google Scholar 

  4. Functional Specification for SystemC 2.0. www.systemc.org (2001)

  5. International technology roadmap for semiconductors (2011) System drivers. Technical report.

    Google Scholar 

  6. Abdallah R, Shanbhag N (2009) Error-resilient low-power Viterbi decoder architectures. IEEE Trans Signal Process 57(12):4906–4917. doi:10.1109/TSP.2009.2026078

    Article  MathSciNet  Google Scholar 

  7. Ansel J, Chan C, Wong YL, Olszewski M, Zhao Q, Edelman A, Amarasinghe S (2009) Petabricks: a language and compiler for algorithmic choice. In: Proceedings of the 30th ACM SIGPLAN conference on programming language design and implementation, PLDI ’09. ACM, New York, pp 38–49. doi:10.1145/1542476.1542481

    Google Scholar 

  8. ARM (2001) ARM AMBA specification and multi layer AHB specification, (rev2.0). http://www.arm.com

  9. Baek W, Chilimbi TM (2010) Green: a framework for supporting energy-conscious programming using controlled approximation. In: Proceedings of the 31st ACM SIGPLAN conference on programming language design and implementation, PLDI ’10. ACM, New York, pp 198–209. doi:10.1145/1806596.1806620

    Chapter  Google Scholar 

  10. Baniasadi A, Moshovos A (2001) Instruction flow-based front end throttling for power-aware high performance processors. In: Proceedings of the 2001 international symposium on Low power electronics and design (ISLPED’01). ACM, New York, pp 16–21. http://dx.doi.org/10.1145/383082.383088

    Google Scholar 

  11. Bansal N, Lahiri K, Raghunathan A, Chakradhar S (2005) Power monitors: a framework for system-level power estimation using heterogeneous power models. In: 18th international conference on VLSI design, pp 579–585 doi:10.1109/ICVD.2005.138

  12. Bhavnagarwala A, Tang X, Meindl J (2001) The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J Solid State Circuits 36(4):658–665. doi:10.1109/4.913744

    Article  Google Scholar 

  13. Blaauw D, Chopra K, Srivastava A, Scheffer L (2008) Statistical timing analysis: from basic principles to state of the art. IEEE Trans Comput Aided Des Integr Circuits Syst 27(4):589–607. doi:10.1109/TCAD.2007.907047

    Article  Google Scholar 

  14. Black J (1969) Electromigration – a brief survey and some recent results. IEEE Trans Electron Devices 16(4):338–347

    Article  Google Scholar 

  15. Blair J, Ghate P, Haywood C (1971) Concerning electromigration in thin films. Proc IEEE lett 59:1023–1024

    Article  Google Scholar 

  16. Breuer M (2010) Hardware that produces bounded rather than exact results. In: 2010 47th ACM/IEEE design automation conference(DAC), Anaheim, pp 871–876

    Google Scholar 

  17. Breuer M, Gupta S, Mak T (2004) Defect and error tolerance in the presence of massive numbers of defects. IEEE Des Test Comput 21(3):216–227. doi:10.1109/MDT.2004.8

    Article  Google Scholar 

  18. Brooks D, Martonosi M (2001) Dynamic thermal management for high-performance microprocessors. In: Proceedings of the 7th international symposium on high-performance computer architecture (HPCA’01). IEEE Computer Society, Washington, DC, p 171

    Google Scholar 

  19. Brooks D, Tiwari V, Martonosi M (2000) Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings of the 27th international symposium on computer architecture, Vancouver, pp 83–94

    Google Scholar 

  20. Cai L, Gajski D (2003) Transaction level modeling: an overview. In: First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, pp 19–24. doi:10.1109/CODESS.2003.1275250

    Google Scholar 

  21. Calhoun B, Chandrakasan A (2004) Standby power reduction using dynamic voltage scaling and canary flip-flop structures. IEEE J Solid State Circuits 39(9):1504–1511. doi:10.1109/JSSC.2004.831432

    Article  Google Scholar 

  22. Calhoun B, Daly D, Verma N, Finchelstein D, Wentzloff D, Wang A, Cho S, Chandrakasan A (2005) Design considerations for ultra-low energy wireless microsensor nodes. IEEE Trans Comput 54(6):727–740. doi:10.1109/TC.2005.98

    Article  Google Scholar 

  23. Calhoun B, Wang A, Chandrakasan A (2005) Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J Solid State Circuits 40(9):1778–1786. doi:10.1109/JSSC.2005.852162

    Article  Google Scholar 

  24. Carbin M, Kim D, Misailovic S, Rinard MC (2012) Proving acceptability properties of relaxed nondeterministic approximate programs. In: Proceedings of the 33rd ACM SIGPLAN conference on programming language design and implementation, PLDI ’12. ACM, New York, pp 169–180. doi:10.1145/2254064.2254086

    Chapter  Google Scholar 

  25. Center for Embedded Computer Systems: SpecC system. http://www.cecs.uci.edu/~specc/

  26. Chabloz J, Hemani A (2010) Distributed DVFS using rationally-related frequencies and discrete voltage levels. In: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED’10). ACM, New York, pp 247–252. http://dx.doi.org/10.1145/1840845.1840897

    Chapter  Google Scholar 

  27. Chakrabarti C, Gaitonde D (1999) Instruction level power model of microcontrollers. In: Proceedings of the 1999 IEEE international symposium on circuits and systems, ISCAS ’99, vol 1, pp 76–79. doi:10.1109/ISCAS.1999.777809

  28. Cho S, Chadrakasan A (2004) A 6.5-ghz energy-efficient BFSK modulator for wireless sensor applications. IEEE J Solid State Circuits 39(5):731–739. doi:10.1109/JSSC.2004.826314

    Article  Google Scholar 

  29. Coskun AK, Rosing TS, Whisnant K (2007) Temperature aware task scheduling in MPSoCS. In: Proceedings of the conference on design, automation and test in Europe (DATE’07). EDA Consortium, San Jose, pp 1659–1664

    Google Scholar 

  30. Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Flautner K, Mudge T (2006) A self-tuning dvs processor using delay-error detection and correction. IEEE J Solid State Circuits 41(4):792–804. doi:10.1109/JSSC.2006.870912

    Article  Google Scholar 

  31. Djahromi A, Eltawil A, Kurdahi F, Kanj R (2007) Cross layer error exploitation for aggressive voltage scaling. In: 8th international symposium on quality electronic design, ISQED ’07, pp 192–197. doi:10.1109/ISQED.2007.53

  32. Donald J, Martonosi M (2005) Leveraging simultaneous multithreading for adaptive thermal control. In: Proceedings of the second workshop on temperature-aware computer systems

    Google Scholar 

  33. Donald J, Martonosi M (2006) Techniques for multicore thermal management: classification and new exploration. ACM SIGARCH computer architecture news. 34(2). IEEE computer society

    Google Scholar 

  34. Eltawil A, Grayver E, Zou H, Frigon J, Poberezhskiy G, Daneshrad B (2003) Dual antenna UMTS mobile station transceiver asic for 2 mb/s data rate. In: IEEE international, solid-state circuits conference on Digest of technical papers, ISSCC 2003, vol 1, pp 146–484. doi:10.1109/ISSCC.2003.1234242

    Google Scholar 

  35. Ernst D, Das S, Lee S, Blaauw D, Austin T, Mudge T, Kim NS, Flautner K (2004) Razor: circuit-level correction of timing errors for low-power operation. IEEE Micro 24(6):10–20. doi:10.1109/MM.2004.85

    Article  Google Scholar 

  36. Gasteier M, Glesner M (1996) Bus-based communication synthesis on system-level. In: Proceedings of 9th international symposium on system synthesis, pp 65–70. doi:10.1109/ISSS.1996.565880

  37. Gerards M, Hurink JL, Kuper J (2015) On the interplay between global DVFS and scheduling tasks with precedence constraints. IEEE Trans Comput 64(6):1742–1754

    MathSciNet  MATH  Google Scholar 

  38. Gronowski P, Bowhill W, Preston R, Gowan M, Allmon R (1998) High-performance microprocessor design. IEEE J Solid State Circuits 33:676–686

    Article  Google Scholar 

  39. Gunther S, Binns F, Carmean D, Hall J (2001) Managing the impact of increasing microprocessor power consumption. Intel Technol J 5:1–9

    Google Scholar 

  40. Herbert S, Marculescu D (2007) Analysis of dynamic voltage/frequency scaling in chip multiprocessors. In: ACM/IEEE international symposium on low power electronics and design (ISLPED). IEEE

    Google Scholar 

  41. Hoffmann H, Sidiroglou S, Carbin M, Misailovic S, Agarwal A, Rinard M (2011) Dynamic knobs for responsive power-aware computing. In: Proceedings of the sixteenth international conference on architectural support for programming languages and operating systems, ASPLOS XVI. ACM, New York, pp 199–212. doi:10.1145/1950365.1950390

    Google Scholar 

  42. HP Labs (2015) CACTI – An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. http://www.hpl.hp.com/research/cacti/

  43. Huang W et al (2006) Hotspot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(5):501–513. doi:10.1109/TVLSI.2006.876103

    Article  Google Scholar 

  44. Hussien A, Khairy M, Khajeh A, Amiri K, Eltawil A, Kurdahi F (2010) A combined channel and hardware noise resilient Viterbi decoder. In: 2010 conference record of the forty fourth Asilomar conference on signals, systems and computers (ASILOMAR), pp 395–399. doi:10.1109/ACSSC.2010.5757543

  45. Im S, Banerjee K (2000) Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs. In: International electron devices meeting 2000. Technical digest. IEDM (Cat. No.00CH37138), San Francisco, pp 727–730.

    Google Scholar 

  46. ITRS International roadmap of semiconductors. http://www.itrs.net/

  47. John JK, Hu JS, Ziavras SG (2005) Optimizing the thermal behavior of subarrayed data caches. In: Proceedings of the 2005 international conference on computer design (ICCD’05). IEEE computer society, Washington, pp 625–630. https://doi.org/10.1109/ICCD.2005.81

    Chapter  Google Scholar 

  48. Kavvadias N, Neofotistos P, Nikolaidis S, Kosmatopoulos K, Laopoulos T (2003) Measurements analysis of the software-related power consumption in microprocessors. In: Proceedings of the 20th IEEE instrumentation and measurement technology conference, IMTC ’03, vol 2, pp 981–986. doi:10.1109/IMTC.2003.1207899

  49. Kaxiras S, Ju Z, Martonosi M (2001) Cache decay: exploiting generational behavior to reduce cache leakage power. In: Proceedings of the 28th annual international symposium on computer architecture (ISCA’01). ACM, New York, pp 240–251. http://dx.doi.org/10.1145/379240.379268

    Google Scholar 

  50. Khajeh A, Cheng SY, Eltawil A, Kurdahi F (2007) Power management for cognitive radio platforms. In: Global telecommunications conference, GLOBECOM ’07. IEEE, pp 4066–4070. doi:10.1109/GLOCOM.2007.773

  51. Khajeh A, Eltawil A, Kurdahi F (2011) Embedded memories fault-tolerant pre- and post-silicon optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(10):1916–1921. doi:10.1109/TVLSI.2010.2056397

    Article  Google Scholar 

  52. Khajeh A, Kim M, Dutt N, Eltawil AM, Kurdahi FJ (2012) Error-aware algorithm/architecture coexploration for video over wireless applications. ACM Trans Embed Comput Syst 11S(1):15:1–15:23. doi:10.1145/2180887.2180892

  53. Kumar A, Shang L, Peh L, Jha NK (2008) System-level dynamic thermal management for high-performance microprocessors. IEEE Trans Comput-Aided Des Integr Circuits Syst 27(1):96–108

    Article  Google Scholar 

  54. Kurdahi F, Eltawil A, Yi K, Cheng S, Khajeh A (2010) Low-power multimedia system design by aggressive voltage scaling. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(5): 852–856. doi:10.1109/TVLSI.2009.2016665

    Article  Google Scholar 

  55. Lahiri K, Raghunathan A, Lakshminarayana G, Dey S (2004) Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans Comput Aided Des Integr Circuits Syst 23(5):620–636. doi:10.1109/TCAD.2004.826585

    Article  Google Scholar 

  56. Lee KJ, Skadron K (2005) Using performance counters for runtime temperature sensing in high-performance processors. In: 19th IEEE international parallel and distributed processing symposium, pp 8. doi:10.1109/IPDPS.2005.448

  57. Lee S, Das S, Pham T, Austin T, Blaauw D, Mudge T (2004) Reducing pipeline energy demands with local DVS and dynamic retiming. In: Proceedings of the 2004 international symposium on low power electronics and design, ISLPED ’04, Newport Beach, pp 319–324.

    Google Scholar 

  58. Lee I, Kim H, Yang P, Yoo S, Chung EY, Choi KM, Kong JT, Eo SK (2006) Powervip: SoC power estimation framework at transaction level. In: Asia and South Pacific conference on design automation, pp 8. doi:10.1109/ASPDAC.2006.1594743

    Google Scholar 

  59. Leem L, Cho H, Bau J, Jacobson Q, Mitra S (2010) Ersa: error resilient system architecture for probabilistic applications. In: Design, automation test in Europe conference exhibition (DATE), pp 1560–1565. doi:10.1109/DATE.2010.5457059

  60. Lienig J (2013) Electromigration and its impact on physical design in future technologies. In: Proceedings of the 2013 ACM international symposium on physical design. ACM, 2013

    Google Scholar 

  61. Liou JJ, Krstic A, Jiang YM, Cheng KT (2000) Path selection and pattern generation for dynamic timing analysis considering power supply noise effects. In: IEEE/ACM international conference on computer aided design, ICCAD-2000, pp 493–496. doi:10.1109/ICCAD.2000.896521

  62. Lloyd JR (1991) Electromigration failure. J Appl Phys 69:7601–7604

    Article  Google Scholar 

  63. Long J, Memik S, Memik G, Mukherjee R (2008) Thermal monitoring mechanisms for chip multiprocessors. ACM Trans Archit Code Optim (TACO) 5(2):9

    Google Scholar 

  64. Macii E, Pedram M, Somenzi F (1998) High-level power modeling, estimation, and optimization. IEEE Trans Comput Aided Des Integr Circuits Syst 17(11):1061–1079. doi:10.1109/43.736181

    Article  Google Scholar 

  65. MacQueen J (1967) Some methods for classification and analysis of multivariate observations. In: Proceedings of the fifth Berkeley symposium on mathematical statistics and probability, vol 1, no 14

    Google Scholar 

  66. Makhzan M, Khajeh A, Eltawil A, Kurdahi F (2007) Limits on voltage scaling for caches utilizing fault tolerant techniques. In: 25th international conference on computer design, ICCD 2007, pp 488–495. doi:10.1109/ICCD.2007.4601943

    Google Scholar 

  67. Mamidipaka M, Khouri K, Dutt N, Abadir M (2004) Analytical models for leakage power estimation of memory array structures. In: International conference on hardware/software codesign and system synthesis, CODES + ISSS 2004, pp 146–151. doi:10.1109/CODESS.2004.240909

  68. Markovic D, Stojanovic V, Nikolic B, Horowitz M, Brodersen R (2004) Methods for true energy-performance optimization. IEEE J Solid-State Circuits 39(8):1282–1293. doi:10.1109/JSSC.2004.831796

    Article  Google Scholar 

  69. Memik SO, Mukherjee R, Ni M, Long J (2008) Optimizing thermal sensor allocation for microprocessors. IEEE Trans Comput Aided Des Integr Circuits Syst 27: 516–527

    Article  Google Scholar 

  70. Misailovic S, Roy D, Rinard M (2011) Probabilistically accurate program transformations. In: Yahav E (ed) Static Analysis. Lecture notes in computer science, vol 6887. Springer, Berlin/Heidelberg, pp 316–333. doi:10.1007/978-3-642-23702-7_24

    Chapter  Google Scholar 

  71. Mukherjee R, Memik SO (2006) Systematic temperature sensor allocation and placement for microprocessors. In: Proceedings of the 43rd annual design automation conference. ACM

    Google Scholar 

  72. Mukherjee R, Mondal S, Memik S (2006) Thermal sensor allocation and placement for reconfigurable systems. In: IEEE/ACM international conference on computer-aided design (ICCAD’06). IEEE

    Google Scholar 

  73. Mukhopadhyay S, Mahmoodi H, Roy K (2004) Statistical design and optimization of SRAM cell for yield enhancement. In: IEEE/ACM international conference on computer aided design, ICCAD-2004, pp 10–13. doi:10.1109/ICCAD.2004.1382534

  74. Mukhopadhyay S, Kim K, Mahmoodi H, Roy K (2007) Design of a process variation tolerant self-repairing SRAM for yield enhancement in nanoscaled CMOS. IEEE J Solid-State Circuits 42(6):1370–1382. doi:10.1109/JSSC.2007.897161

    Article  Google Scholar 

  75. Mukhopadhyay S, Mahmoodi H, Roy K (2008) Reduction of parametric failures in sub-100-nm SRAM array using body bias. IEEE Trans Comput Aided Des Integr Circuits Syst 27(1):174–183. doi:10.1109/TCAD.2007.906995

    Article  Google Scholar 

  76. Noble B (2000) System support for mobile, adaptive applications. IEEE Pers Commun 7(1):44–49. doi:10.1109/98.824577

    Article  Google Scholar 

  77. Nowroz A, Cochran R, Reda S (2010) Thermal monitoring of real processors: techniques for sensor allocation and full characterization. In: Proceedings of the 47th design automation conference. ACM

    Google Scholar 

  78. Onouchi M, Yamada T, Morikawa K, Mochizuki I, Sekine H (2006) A system-level power-estimation methodology based on ip-level modeling, power-level adjustment, and power accumulation. In: Asia and South Pacific conference on design automation, pp 4. doi:10.1109/ASPDAC.2006.1594742

    Google Scholar 

  79. Orio Rd, Ceric H, Selberherr S (2010) Physically based models of electromigration: from black’s equation to modern TCAD models. Microelectron Reliab 50:775–789

    Article  Google Scholar 

  80. Park YH, Pasricha S, Kurdahi F, Dutt N (2007) System level power estimation methodology with h.264 decoder prediction IP case study. In: 25th international conference on computer design, ICCD 2007, pp 601–608. doi:10.1109/ICCD.2007.4601959

    Google Scholar 

  81. Park Y, Pasricha S, Kurdahi F, Dutt N (2008) Methodology for multi-granularity embedded processor power model generation for an ESL design flow. IEEE/ACM CODES+ISSS

    Book  Google Scholar 

  82. Pasricha S, Dutt N, Ben-Romdhane M (2004) Extending the transaction level modeling approach for fast communication architecture exploration. In: Proceedings of 41st design automation conference, New York, pp 113–118

    Google Scholar 

  83. Pasricha S, Dutt N, Ben-Romdhane M (2006) Constraint-driven bus matrix synthesis for MPSoC. In: Asia and South Pacific conference on design automation, pp 6. doi:10.1109/ASPDAC.2006.1594641

    Google Scholar 

  84. Pasricha S, Park YH, Kurdahi F, Dutt N (2006) System-level power-performance trade-offs in bus matrix communication architecture synthesis. In: Proceedings of the 4th international conference hardware/Software codesign and system synthesis, CODES + ISSS ’06, pp 300–305. doi:10.1145/1176254.1176327

  85. Pinto A, Carloni L, Sangiovanni-Vincentelli A (2003) Efficient synthesis of networks on chip. In: Proceedings of 21st international conference on computer design, pp 146–150. doi:10.1109/ICCD.2003.1240887

  86. Powell MD, Biswas A, Emer JS, Mukherjee S, Sheikh B, Yardi S (2009) Camp: a technique to estimate per-structure power at run-time using a few simple parameters. In: IEEE 15th international symposium on high performance computer architecture (HPCA’09). IEEE

    Google Scholar 

  87. Rabaey JM (1996) Digital integrated circuits: a design perspective. Prentice-Hall, Inc., Upper Saddle River

    Google Scholar 

  88. Rao R, Vrudhula S, Chakrabarti C (2007) Throughput of multi-core processors under thermal constraints. In: Proceedings of the 2007 international symposium on low power electronics and design. ACM

    Google Scholar 

  89. Ravi S, Raghunathan A, Chakradhar S (2003) Efficient RTL power estimation for large designs. In: Proceedings of 16th international conference on VLSI design, pp 431–439. doi:10.1109/ICVD.2003.1183173

  90. Rinard M (2006) Probabilistic accuracy bounds for fault-tolerant computations that discard tasks. In: Proceedings of the 20th annual international conference on supercomputing, ICS ’06. ACM, New York, pp 324–334. doi:10.1145/1183401.1183447.

    Chapter  Google Scholar 

  91. Rinard M, Hoffmann H, Misailovic S, Sidiroglou S (2010) Patterns and statistical analysis for understanding reduced resource computing. In: Proceedings of the ACM international conference on object oriented programming systems languages and applications, OOPSLA ’10. ACM, New York, pp 806–821. doi:10.1145/1869459.1869525

    Chapter  Google Scholar 

  92. Rodriguez S, Jacob B (2006) Energy/power breakdown of pipelined nanometer caches (90 nm/65 nm/45 nm/32 nm). In: Proceedings of the 2006 international symposium on low power electronics and design, ISLPED’06, pp 25–30. doi:10.1109/LPE.2006.4271802

  93. Rohou E, Smith M (1999) Dynamically managing processor temperature and power. In: 2nd workshop on feedback-directed optimization

    Google Scholar 

  94. Sami M, Sciuto D, Silvano C, Zaccaria V (2000) Instruction-level power estimation for embedded VLIW cores. In: Proceedings of the eighth international workshop on hardware/software codesign, CODES 2000, San Diego, pp 34–38

    Google Scholar 

  95. Sampson A, Dietl W, Fortuna E, Gnanapragasam D, Ceze L, Grossman D (2011) Enerj: approximate data types for safe and general low-power computation. In: Proceedings of the 32nd ACM SIGPLAN conference on programming language design and implementation, PLDI ’11. ACM, New York, pp 164–174. doi:10.1145/1993498.1993518

  96. Sanchez H, Philip R, Alvarez J, Gerosa G (1997) A CMOS temperature sensor for PowerPC RISC microprocessors. In: Proceedings of the symposium on VLSI circuits. IEEE, pp 13–14

    Google Scholar 

  97. Sarrigeorgidis K, Rabaey J (2004) Ultra low power cordic processor for wireless communication algorithms. J VLSI Signal Process Syst Signal Image Video Technol 38(2):115–130. doi:10.1023/B:VLSI.0000040424.11334.34

    Article  Google Scholar 

  98. Sarta D, Trifone D, Ascia G (1999) A data dependent approach to instruction level power estimation. In: Proceedings of IEEE Alessandro volta memorial workshop on low-power design, pp 182–190. doi:10.1109/LPD.1999.750419

    Google Scholar 

  99. Shanbhag N(2002) Reliable and energy-efficient digital signal processing. In: Proceedings of 39th design automation conference, pp 830–835. doi:10.1109/DAC.2002.1012737

  100. Shatzkes M, Lloyd JR (1986) A model for conductor failure considering diffusion concurrently with electromigration resulting in a current exponent of 2. J Appl Phys 59, 3890–3893

    Article  Google Scholar 

  101. Shin JY, Kurdahi F, Dutt N (2015) Cooperative on-chip temperature estimationusing multiple virtual sensors. IEEE Embed Syst Lett 7(2):37–40. doi:10.1109/LES.2015.2400992

    Article  Google Scholar 

  102. Skadron K, Stan MR, Huang W, Velusamy S, Sankaranarayanan K, Tarjan D (2003) Temperature-aware computer systems: opportunities and challenges. IEEE Micro 23(6): 52–61

    Article  Google Scholar 

  103. Skadron K, Stan M, Sankaranarayanan K, Huang W, Velusamy S, Tarjan D (2004) Temperature-aware microarchitecture: modeling and implementation. ACM Trans Archit Code Optim 1:94–125

    Article  Google Scholar 

  104. Sloan J, Sartori J, Kumar R (2012) On software design for stochastic processors. In: Proceedings of the 49th annual design automation conference, DAC ’12. ACM, New York, pp 918–923. doi:10.1145/2228360.2228524

    Chapter  Google Scholar 

  105. Uht A (2004) Going beyond worst-case specs with teatime. Computer 37(3):51–56. doi:10.1109/MC.2004.1274004

    Article  Google Scholar 

  106. Wan L, Chen D (2010) Analysis of circuit dynamic behavior with timed ternary decision diagram. In: 2010 IEEE/ACM international conference on computer-aided design (ICCAD), pp 516–523. doi:10.1109/ICCAD.2010.5653852

  107. Wang H, Tan S, Swarup S, Liu X (2013) A power-driven thermal sensor placement algorithm for dynamic thermal management. In: Design, automation & test in Europe conference & exhibition (DATE’13). IEEE

    Google Scholar 

  108. Wu W, Jin L, Yang J, Liu P, Tan S (2006) A systematic method for functional unit power estimation in mircoprocessors. In: 2006 43rd ACM/IEEE on design automation conference. IEEE

    Google Scholar 

  109. Ye W, Vijaykrishnan N, Kandemir M, Irwin M (2000) The design and use of simplepower: a cycle-accurate energy estimation tool. In: Proceedings of 2000 design automation conference, pp 340–345. doi:10.1109/DAC.2000.855333

  110. Zaynoun S, Khairy M, Eltawil A, Kurdahi F, Khajeh A (2012) Fast error aware model for arithmetic and logic circuits. In: 2012 IEEE 30th international conference on computer design (ICCD), pp 322–328. doi:10.1109/ICCD.2012.6378659

  111. Zhang Y, Li Y, Li X, Yao SC (2013) Strip-and-zone micro-channel liquid cooling of integrated circuits chips with non-uniform power distributions. In: ASME 2013 heat transfer summer conference

    Google Scholar 

  112. Zhang Y, Shi B, Srivastava A (2010) A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems. IEEE Trans Very Large Scale Integration (VLSI) Syst 22(2):270–279

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Digital Media and Communications R&D Center, Samsung Electronics, Seoul, Korea

    Young-Hwan Park

  2. Broadcom Corp., San Jose, CA, USA

    Amin Khajeh

  3. Center for Embedded and Cyber-Physical Systems, University of California Irvine, 92697, Irvine, CA, USA

    Jun Yong Shin, Fadi Kurdahi, Ahmed Eltawil & Nikil Dutt

Authors
  1. Young-Hwan Park
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Amin Khajeh
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jun Yong Shin
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Fadi Kurdahi
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Ahmed Eltawil
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Nikil Dutt
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Fadi Kurdahi .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer Science+Business Media Dordrecht

About this entry

Cite this entry

Park, YH., Khajeh, A., Shin, J.Y., Kurdahi, F., Eltawil, A., Dutt, N. (2017). Microarchitecture-Level SoC Design. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_28

Download citation

Publish with us

Policies and ethics

Search

Navigation