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Microarchitecture-Level SoC Design

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In this chapter we consider the issues related to integrating microarchitectural IP blocks into complex SoCs while satisfying performance, power, thermal, and reliability constraints. We first review different abstraction levels for SoC design that promote IP reuse, and which enable fast simulation for early functional validation of the SoC platform. Since SoCs must satisfy a multitude of interrelated constraints, we then present high-level power, thermal, and reliability models for predicting these constraints. These constraints are not unrelated and their interactions must be considered, modeled and evaluated. Once constraints are modeled, we must explore the design space trading off performance, power and reliability. Several case studies are presented illustrating how the design space can be explored across layers, and what modifications could be applied at design time and/or runtime to deal with reliability issues that may arise.

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  • DOI: 10.1007/978-94-017-7267-9_28
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Advanced High-performance Bus


Advanced Peripheral Bus


Application-Specific Integrated Circuit


Bit Error Rate


Bit Lock Block


Cycle Accurate


Code Division Multiple Access


Complementary Metal-Oxide-Semiconductor


Chip Multi-Processor


Central Processing Unit


Dynamic Frequency Scaling


Direct Memory Access


Dynamic Timing Analysis


Dynamic Thermal Management


Dynamic Voltage and Frequency Scaling


Dynamic Voltage Scaling


Electronic System Level


General-Purpose Input/Output-pin


Inquisitive Defect Cache


Intellectual Property


Intellectual Property Block


Instruction-Set Simulator


International Technology Roadmap for Semiconductors


Metal-Oxide-Semiconductor Field-Effect Transistor


Multi-Processor System-on-Chip


Mean Time to Failure


Negative-type Metal-Oxide-Semiconductor


Probability Density Function


Principal Investigator


Positive-type Metal-Oxide-Semiconductor


Peak SNR


Random-Access Memory


Random Dopant Fluctuations


Read-Only Memory


Register Transfer Level


Signal-to-Noise Ratio




Static Random-Access Memory


Statistical Static Timing Analysis


Transaction-based Bus Cycle Accurate


Transaction-Level Model


Voltage/Frequency Island


Voltage Over Scaling


Wideband CDMA


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Correspondence to Fadi Kurdahi .

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Park, YH., Khajeh, A., Shin, J.Y., Kurdahi, F., Eltawil, A., Dutt, N. (2017). Microarchitecture-Level SoC Design. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht.

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