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MRAM Circuits

  • Shinobu FujitaEmail author
Reference work entry

Abstract

This chapter describes MRAM circuits, including basic circuit designs for random access memory, MRAM circuits with magnetic field, and advanced spin-based-NVRAM circuits without magnetic field. Major point for the memory circuit design is a write operation of MRAM. It also explains read circuit design for fast and stable read operation of MRAM to avoid read disturbance. Finally, there are many issues of MRAM circuit design from the viewpoints of memory area, memory performance, and power. From the application point of views, active power of MTJ has to be largely decreased by improving MTJ performance and designing low-power-memory circuits.

Keywords

Memory Cell Reference Cell Nonvolatile Memory Domain Wall Motion Read Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

List of Abbreviations

BL

Bit line

CMOS

Complementary metal oxide Semiconductor

DRAM

Dynamic random access memory

MRAM

Magnetic random access memory

MTJ

Magnetic tunneling junction

NVM

Nonvolatile memory

RAM

Random access memory

SA

Sense amplifier

SRAM

Static random access memory

SRAM

Static random access memory

STT

Spin-transfer torque

TMR

Tunnel magnetoresistance

TMR

Tunnel magnetoresistance

References

  1. 1.
    Peter K et al (2001) A 256kb 3.0V 1T1MTJ nonvolatile magnetoresistive RAM. ISSCC digest of technical papers, Paper number 7.6, Feb 2001, pp122–123Google Scholar
  2. 2.
    Iwata Y et al (2006) A 16 Mb MRAM with FORK wiring scheme and burst modes. ISSCC digest of technical papers, Paper number 7.4, Feb 2006Google Scholar
  3. 3.
    Nahas J et al (2004) A 4 Mb 0.18 μm 1T1MTJ toggle MRAM memory. ISSCC digest of technical papers, Paper number 2.3, Feb 2004Google Scholar
  4. 4.
    Sakiumura N et al (2007) A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture. In: IEEE Asian solid-state circuits conference digest of technical papers, Kyoto, Japan, Nov 2007, pp 216–219Google Scholar
  5. 5.
    Nebashi R et al (2008) A 90nm 12ns 32Mb 2T1MTJ MRAM. ISSCC digest of technical papers, Paper number 27.4, Feb 2009Google Scholar
  6. 6.
    Sakiumura N et al (2008) A 500-MHz MRAM macro for high-performance SoCs. In: IEEE Asian solid-state circuits conference digest of technical papers, Fukuoka, Japan, Nov 2008, pp 261–264Google Scholar
  7. 7.
    Kawahara T (2007) 2Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read. ISSCC digest of technical papers, Paper number 26.5, Feb 2007Google Scholar
  8. 8.
    Takemura R (2009) 32-Mb 2T1R SPRAM with localized bi-directional write driver and “1”/“0” dual-array equalized reference cell. In: Symposium on VLSI circuits digest of technical papers, Kyoto, Japan, pp 84–85Google Scholar
  9. 9.
    Tsuchida K et al (2010) A 64 Mb MRAM with clamped-reference and adequate-reference schemes ISSCC digest of technical papers. Scalable cell technology utilizing domain wall motion for high-speed MRAM, Paper number 14.2, Feb 2010Google Scholar
  10. 10.
    Fukami S et al (2009) Low-current perpendicular domain wall motion cell for scalable high-speed MRAM. In: Symposium on VLSI technology digest of technical papers, Hershey, Kyoto, Japan, pp 230–231Google Scholar
  11. 11.
    Kim JP et al A 45 nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance. In: Symposium on VLSI circuits digest of technical papers, Kyoto, Japan, pp 296–297Google Scholar
  12. 12.
    Chen E (2012) Progress and prospects of spin transfer torque random access memory. IEEE Trans Magn 48(11):3025–3030CrossRefADSGoogle Scholar
  13. 13.
    Ando K et al (2012) Roles of non-volatile devices in future computer system: normally-off computer. In: Kaabouch N, Hu W-C (eds) Energy-aware systems and networking for sustainable initiatives. IGI Global, IEEEGoogle Scholar
  14. 14.
    Nomura K et al (2012) Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers. J Appl Phys 111(7) pp. 07E329-1 – 07E329-3.Google Scholar
  15. 15.
    Abe K et al (2010) Hierarchical cache memory based on MRAM and nonvolatile SRAM with perpendicular magnetic tunnel junctions for ultra low power system. In: International conference on solid state devices and materials(SSDM), Tokyo, Japan, Sept 2010, pp 1144–1145Google Scholar
  16. 16.
    Abe K, Fujita S, Lee TH (2005) Novel nonvolatile logic circuits with three-dimensionally stacked nanoscale memory device. In: NSTI nanotechnology conference, Anaheim, vol 3, pp 203–206Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2016

Authors and Affiliations

  1. 1.Toshiba Corporate R & D CenterKawasakiJapan

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