Skip to main content
SpringerLink
Log in
Book cover

Encyclopedia of Algorithms pp 1–6Cite as

Analyzing Cache Behaviour in Multicore Architectures

  • Living reference work entry
  • First Online:

  • 331 Accesses

Years and Authors of Summarized Original Work

2010; Hassidim

2012; López-Ortiz, Salinger

Problem Definition

Multicore processors are commonly equipped with one or more levels of cache memory, some of which are shared among two or more cores. Multiple cores compete for the use of shared caches for fast access to their program’s data, with the cache usage patterns of a program running on one core, possibly affecting the cache performance of programs running on other cores.

Paging

The management of data across the various levels of the memory hierarchy of modern computers is abstracted by the paging problem. Paging models a two-level memory system with a small and fast memory – known as cache – and a large and slow memory. Data is transferred between the two levels of memory in units known as pages. The input to the problem is a sequence of page requests that must be made available in cache as they are requested. If the currently requested page is already present in the cache, then this...

This is a preview of subscription content, log in via an institution.

Recommended Reading

  1. Barve RD, Grove EF, Vitter JS (2000) Application-controlled paging for a shared cache. SIAM J Comput 29:1290–1303

    Article  MATH  MathSciNet  Google Scholar 

  2. Borodin A, El-Yaniv R (1998) Online computation and competitive analysis. Cambridge University Press, New York

    MATH  Google Scholar 

  3. Cao P, Felten EW, Li K (1994) Application-controlled file caching policies. In: Proceedings of the USENIX summer 1994 technical conference – volume 1 (USTC’94), Boston, pp 171–182

    Google Scholar 

  4. Feuerstein E, Strejilevich de Loma A (2002) On-line multi-threaded paging. Algorithmica 32(1):36–60

    Article  MATH  MathSciNet  Google Scholar 

  5. Fiat A, Karlin AR (1995) Randomized and multipointer paging with locality of reference. In: Proceedings of the 27th annual ACM symposium on theory of computing (STOC’95), Las Vegas. ACM, pp 626–634

    Google Scholar 

  6. Hassidim A (2010) Cache replacement policies for multicore processors. In: Yao ACC (ed) Innovations in computer science (ICS 2010), Tsinghua University, Beijing, 2010, pp 501–509

    Google Scholar 

  7. Katti AK, Ramachandran V (2012) Competitive cache replacement strategies for shared cache environments. In: International parallel and distributed processing symposium, Shanghai, pp 215–226

    Google Scholar 

  8. López-Ortiz A, Salinger A (2012) Paging for multi-core shared caches. In: Proceedings of the 3rd innovations in theoretical computer science conference (ITCS’12), Cambridge. ACM, pp 113–127

    Google Scholar 

  9. Peserico E (2013) Elastic paging. In: SIGMETRICS, Pittsburgh. ACM, pp 349–350

    Google Scholar 

  10. Sleator DD, Tarjan RE (1985) Amortized efficiency of list update and paging rules. Commun ACM 28(2):202–208

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. David R. Cheriton School of Computer Science, University of Waterloo, Waterloo, ON, Canada

    Alejandro López-Ortiz

  2. Department of Computer Science, Saarland University, Saarbücken, Germany

    Alejandro Salinger

Authors
  1. Alejandro López-Ortiz
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Alejandro Salinger
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Alejandro López-Ortiz .

Editor information

Editors and Affiliations

  1. Dept. Electrical Engineering & Computer Science, Northwestern University, Evanston, Illinois, USA

    Ming-Yang Kao

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer Science+Business Media New York

About this entry

Cite this entry

López-Ortiz, A., Salinger, A. (2014). Analyzing Cache Behaviour in Multicore Architectures. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-3-642-27848-8_534-1

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-27848-8_534-1

  • Received:

  • Accepted:

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Online ISBN: 978-3-642-27848-8

  • eBook Packages: Springer Reference Computer SciencesReference Module Computer Science and Engineering

Publish with us

Policies and ethics

Search

Navigation