Encyclopedia of Algorithms

Living Edition
| Editors: Ming-Yang Kao

Analyzing Cache Behaviour in Multicore Architectures

  • Alejandro López-OrtizEmail author
  • Alejandro  Salinger
Living reference work entry
DOI: https://doi.org/10.1007/978-3-642-27848-8_534-1

Years and Authors of Summarized Original Work

2010; Hassidim

2012; López-Ortiz, Salinger

Problem Definition

Multicore processors are commonly equipped with one or more levels of cache memory, some of which are shared among two or more cores. Multiple cores compete for the use of shared caches for fast access to their program’s data, with the cache usage patterns of a program running on one core, possibly affecting the cache performance of programs running on other cores.

Paging

The management of data across the various levels of the memory hierarchy of modern computers is abstracted by the paging problem. Paging models a two-level memory system with a small and fast memory – known as cache – and a large and slow memory. Data is transferred between the two levels of memory in units known as pages. The input to the problem is a sequence of page requests that must be made available in cache as they are requested. If the currently requested page is already present in the cache, then this...

Keywords

Multicore Chip multiprocessor Cache Paging Online algorithms 
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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.David R. Cheriton School of Computer Science, University of WaterlooWaterloo, ONCanada
  2. 2.Department of Computer Science, Saarland UniversitySaarbückenGermany