Encyclopedia of Algorithms

2008 Edition
| Editors: Ming-Yang Kao

Floorplan and Placement

1994; Kajitani, Nakatake, Murata, Fujiyoshi
  • Yoji Kajitani
Reference work entry
DOI: https://doi.org/10.1007/978-0-387-30162-4_145

Keywords and Synonyms

Layout ; Alignment ; Packing; Dissection

Problem Definition

The problem is concerned with efficient coding of the constraint that defines the placement of objects on a plane without mutual overlapping. This has numerous motivations, especially in the design automation of integrated semiconductor chips, where almost hundreds of millions of rectangular modules shall be placed within a small rectangular area (chip). Until 1994, the only known coding efficient in computer aided design was Polish‐Expression [1]. However, this can only handle a limited class of placements of the slicing structure. In 1994 Nakatake, Fujiyoshi, Murata, and Kajitani [2], and Murata, Fujiyoshi, Nakatake, and Kajitani [3] were finally successful to answer this longstanding problem in two contrasting ways. Their code names are Bounded‐Sliceline-Grid (BSG) for floorplanning and Sequence-Pair (SP) for placement.         


1. Floorplanning, placement, compaction, packing, layout:Often...


Layout Problem Area Placement Simple Data Structure Analog Circuit Design Nonoverlapping Constraint 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Recommended Reading

  1. 1.
    Wong, D.F., Liu, C.L.: A new algorithm for floorplan design. In: ACM/IEEE Design Automation Conference (DAC), November 1985, 23rd, pp. 101–107Google Scholar
  2. 2.
    Nakatake, S., Murata, H., Fujiyoshi, K., Kajitani, Y.: Bounded Sliceline Grid (BSG) for module packing. IEICE Technical Report, October 1994, VLD94-66, vol. 94, no. 313, pp. 19–24 (in Japanese)Google Scholar
  3. 3.
    Murata, H., Fujiyoshi, K., Nakatake, S., Kajitani, Y.: A solution space of size (n!)2 for optimal rectangle packing. In: 8th Karuizawa Workshop on Circuits and Systems, April 1995, pp. 109–114Google Scholar
  4. 4.
    Murata, H., Nakatake, S., Fujiyoshi, K., Kajitani, Y.: VLSI Module placement based on rectangle‐packing by Sequence-Pair. IEEE Trans. Comput. Aided Design (TCAD) 15(12), 1518–1524 (1996)CrossRefGoogle Scholar
  5. 5.
    Nakatake, S., Fujiyoshi, K., Murata, H., Kajitani, Y.: Module packing based on the BSG‐structure and IC layout applications. IEEE TCAD 17(6), 519–530 (1998)Google Scholar
  6. 6.
    Guo, P.N., Cheng, C.K., Yoshimura, T.: An O‑tree representation of non-slicing floorplan and its applications. In: 36th DAC., June 1998, pp. 268–273Google Scholar
  7. 7.
    Hong, X., Dong, S., Ma, Y., Cai, Y., Cheng, C.K., Gu, J.: Corner Block List: An efficient topological representation of non-slicing floorplan. In: International Computer Aided Design (ICCAD) '00, November 2000, pp. 8–12,Google Scholar
  8. 8.
    Chang, Y.-C., Chang, Y.-W., Wu, G.-M., Wu, S.-W.: B*-trees: A new representation for non-slicing floorplans. In: 37th DAC, June 2000, pp. 458–463Google Scholar
  9. 9.
    Sakanushi, K., Kajitani, Y., Mehta, D.: The quarter-state-sequence floorplan representation. In: IEEE TCAS-I: 50(3), 376–386 (2003)Google Scholar
  10. 10.
    Kodama, C., Fujiyoshi, K.: Selected Sequence-Pair: An efficient decodable packing representation in linear time using Sequence-Pair. In: Proc. ASP-DAC 2003, pp. 331–337Google Scholar
  11. 11.
    Kajitani, Y.: Theory of placement by Single‐Sequence Realted with DAG, SP, BSG, and O‑tree. In: International Symposium on Circuts and Systems, May 2006Google Scholar
  12. 12.
    Imahori, S.: Privatre communication, December 2005Google Scholar

Copyright information

© Springer-Verlag 2008

Authors and Affiliations

  • Yoji Kajitani
    • 1
  1. 1.Department of Information and Media SciencesThe University of KitakyushuKitakyushuJapan