Encyclopedia of Parallel Computing

2011 Edition
| Editors: David Padua

Power Wall

  • Pradip Bose
Reference work entry
DOI: https://doi.org/10.1007/978-0-387-09766-4_499


The “Power Wall” refers to the difficulty of scaling the performance of computing chips and systems at historical levels, because of fundamental constraints imposed by affordable power delivery and dissipation. The single biggest factor that has led the industry into encountering this wall in the past decade is the significant change in traditional CMOS chip design evolution, which were driven previously by Dennard scaling rules [515].



Power delivery and dissipation limits have emerged as a key constraint in the design of microprocessors and associated systems even for those targeted for the high end server product space. At the low end of the performance spectrum, power has always dominated over performance as the primary design constraint. However, while battery life expectancies have shown modest increases, the larger demand for increased functionality and speed has increased the severity of the power constraint in the world of handheld and...

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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Pradip Bose
    • 1
  1. 1.Reliability & Power-Aware MicroarchitecturesIBM Corp. T.J. Watson Research CenterYorktown HeightsUSA