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Power Wall

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Encyclopedia of Parallel Computing

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Bibliography

  1. Agrawal A, Mukhopadhyay S, Raychowdhury A, Roy K, Kim CH (2006) Leakage power analysis and reduction in nanoscale circuits. IEEE Micro 26(2):68–80

    Google Scholar 

  2. Albonesi D (1998) Dynamic IPC/clock rate optimization. In: Proceedings of the 25th annual international symposium on computer architecture (ISCA), ACM/IEEE Computer Society, Barcelona, pp 282–292

    Google Scholar 

  3. Albonesi DH, Balasubramonian R, Dropsho SG, Dwarkadas S, Friedman EG, Huang MC, Kursun V, Magklis G, Scott ML, Semeraro G, Bose P, Buyuktosunoglu A, Cook PW, Schuster SE (2003) Dynamically tuning processor resources with adaptive processing. IEEE Comput 36(12):49–58, Special Issue on Power-Aware Computing

    Google Scholar 

  4. Barroso L, Holzle U (2007) The case for energy proportional computing. IEEE Comput 40(12):33–37

    Google Scholar 

  5. Bohr M (2007) A 30 year retrospective on dennard’s MOSFET scaling paper. P Solid St Circ Soc 12(1):11–13

    Google Scholar 

  6. Borkar S (1999) Design challenges of technology scaling. P IEEE Micro 19(4):23–29

    Google Scholar 

  7. Bose P, Kim S, O’Connell FP (1999) Ciarfella WA Bounds modeling and compiler optimizations for superscalar performance tuning. J Syst Architect 45:1111–1137; Elsevier

    Google Scholar 

  8. Brews JR (1979) Subthreshold behavior of uniformly and non-uniformly doped long-channel MOSFET. IEEE T Electron Dev 26:1282–1291

    Google Scholar 

  9. Brooks D, Bose P, Srinivasan V, Gschwind MK, Emma PG, Rosenfield MG (2003) New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. IBM J Res Dev 47(5/6):653–662

    Google Scholar 

  10. Brooks D, Martonosi M (1999) Dynamically exploiting narrow width operands to improve processor power and performance. In: Proceedings of the 5th international symposium on high-performance computer architecture (HPCA-5), IEEE Computer Society, Orlando

    Google Scholar 

  11. Brooks D, Martonosi M (2001) Dynamic thermal management for high-performance microprocessors. In: Proceedings of the 7th internatinal symposium On high performance computer architecture, IEEE Computer Society, Nuevo Leone, pp 20–24

    Google Scholar 

  12. Brooks DM, Bose P, Schuster SE, Jacobson H, Kudva PN, Buyuktosunoglu A, Wellman J-D, Zyuban V, Gupta M, Cook PW (2000) Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors. P IEEE Micro 20(6):26–44

    Google Scholar 

  13. Buyuktosunoglu A et al (2000) An adaptive issue queue for reduced power at high performance. In: Proceedings ISCA Workshop on complexity-effective design (WCED), Vancouver

    Google Scholar 

  14. Cruz J-L, Gonzalez A, Valero M, Topham NP (2000) Multiple-banked register file architectures. In: Proceedings of the international symposium on computer architecture (ISCA), Vancouver, pp 316–325

    Google Scholar 

  15. Dennard R et al (1974) Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J Solid St Circ SC-9(5):256–268

    Google Scholar 

  16. Diefendorff K (1999) POWER4 focuses on memory bandwidth. Microprocessor Report 13(13):11–17

    Google Scholar 

  17. Dubey PK, Flynn MJ (1990) Optimal pipelining. J Parallel Distr Com 8(1):10–19

    Google Scholar 

  18. Flautner K, Kim NS, Martin S, Blaauw D, Mudge T (2002) Drowsy Caches: simple techniques for reducing leakage power. In: Proceedings of the international symposium on computer architecture (ISCA), IEEE Computer Society, Anchorage

    Google Scholar 

  19. Flynn MJ, Hung P, Rudd K (1999) Deep-submicron microprocessor design issues. P IEEE Micro 19(4):11–22

    Google Scholar 

  20. Gara A et al (2005) Overview of the blue gene/L system architecture. IBM J Res Dev 49(2/3):195–212

    Google Scholar 

  21. Gonzalez R, Horowitz M (1996) Energy dissipation in general purpose microprocessors. IEEE J Solid-St Circ 31(9):1277–1284

    Google Scholar 

  22. Grunwald D, Klauser A, Manne S, Pleszkun, A (1998) Confidence estimation for speculation control. In: Proceedings 25th annual international symposium on computer architecture (ISCA), ACM/IEEE Computer Society, Barcelona, pp 122–131

    Google Scholar 

  23. Gunther SH, Binns F, Carmean DM, Hall JC (2000) Managing the impact of increasing microprocessor power consumption. In: Proceedings of the Intel Technology Journal

    Google Scholar 

  24. Hartstein A, Puzak TR (2002) The optimum pipeline depth for a microprocessor. Proceedings of the 29th international symposium on computer architecture (ISCA-29), IEEE Computer Society, Anchorage

    Google Scholar 

  25. http://www.specbench.org

  26. Hu C (1996) Device and technology impact on low power electronics. In: Rabaey J (ed) Low power design methodologies. Kluwer, Boston, pp 21–35

    Google Scholar 

  27. Hu Z, Buyuktosunoglu A, Srinivasan V, Zyuban V, Jacobson H, Bose P (2004) Microarchitectural techniques for power gating of execution units. In: Proceedings of the international symposium on low power electronics and design (ISLPED), ACM, Newport Beach

    Google Scholar 

  28. ISSCC (International Solid State Circuits Conference) (2010) Trends Report, http://isscc.org/doc/2010/ISSCC2010∖_TechTrends.pdf

  29. Iyer A, Marculescu D (2002) Power-performance evaluation of globally asynchronous, locally synchronous processors. In: Proceedings of the international symposium on computer architecture (ISCA), IEEE Computer Society, Anchorage

    Google Scholar 

  30. Jacobson H, Bose P, Hu Z, Eickemeyer R, Eisen L, Griswell J (2005) Stretching the limits of clock-gating efficiency in server-class processors. In: Proceedngs of the international symposium on high performance computer architecture (HPCA), IEEE Computer Society, San Francisco

    Google Scholar 

  31. Jacobson HM (2004) Improved clock-gating through transparent pipelining. In: Proceedings of the international symposium on low Power electronics and design (ISLPED), ACM, California

    Google Scholar 

  32. Jacobson HM et al (2002) Synchronous interlocked pipelines. In: Proceedings of the international symposium on advanced research in asynchronous circuits and systems, IEEE Computer Society, Manchester

    Google Scholar 

  33. Kahle JA et al (2005) Introduction to the Cell multiprocessor. IBM J Res Dev 49(4/5):589–604

    Google Scholar 

  34. Kalla R, Sinharoy B, Starke WJ, Floyd MJ (2010) Power7: IBM’s next generation server processor. IEEE Micro 30(2):7–15

    Google Scholar 

  35. Kalla R, Sinharoy B, Tendler J (2004) IBM POWER5 chip: a dual-core multithreaded processor, IEEE Micro 24(2):40–47

    Google Scholar 

  36. Kanda K et al (2001) Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. IEEE JSSC, 36(10):1559–1564

    Google Scholar 

  37. Karkhanis T, Bose P, Smith J (2002) Saving energy with just in time instruction delivery. In: Proceedings of the intenational symposium on low power electronics and design (ISLPED), ACM, Monterey

    Google Scholar 

  38. Kaxiras S, Hu Z, Martonosi M (2001) Cache Decay: exploiting generational behavior to reduce cache leakage power. In: Proceedings of the international symposium on computer architecture (ISCA), Goteborg

    Google Scholar 

  39. Kogge PM (1981) The architecture of pipelined computers. Hemisphere Publishing Corporation, New York

    MATH  Google Scholar 

  40. Kongetira P (2004) A 32-way multithreaded SPARC® processor. Presented at Hot Chips

    Google Scholar 

  41. Kumar R, Tullsen D, Jouppi N, Ranganathan P (2005) Heterogeneous chip multiprocessors. IEEE Comput 38(11):32–38

    Google Scholar 

  42. Larson AG (1973) Cost-effective processor design with an application to fast fourier transform computers. Digital systems laboratory report SU-SEL-73-037, Stanford University, Stanford; see also, Larson and Davidson (1973) Cost-effective design of special purpse processors: a fast fourier transform case study. In: Proceedings 11th annual allerton conference on circuits and system theory. University of Illinois, Champaihn-Urbana, pp 547–557

    Google Scholar 

  43. Leverich J, Monchiero M, Talwar V, Ranganathan P, Kozyrakis C (2009) Power management of datacenter workloads using per-core power gating. IEEE Comput Archit Lett 8(2): 48–51

    Google Scholar 

  44. Lungu A, Bose P, Buyuktosunoglu A, Sorin D (2009) Dynamic power gating with quality guarantees. In: Proceedings of the international symposium on low power electronics and design (ISLPED), ACM, New York

    Google Scholar 

  45. Madan NS, Buyuktosunoglu A, Bose P, Annavaram M (2011) Guarded power gating in a multi-core setting, presented at ISCA workshop on energy-efficient design (WEED), June 2010; to appear as a Lecture notes on computer science (LNCS) volume in 2010; see also full paper in Proceedings of the 17th international Symposium on high performance computer architecture (HPCA)

    Google Scholar 

  46. Manne S, Klauser A, Grunwald D (1998) Pipeline gating: speculation control for energy reduction. In: Proceedings of the 25th annual international symposium on computer architecture (ISCA), ACM/IEEE Computer Society, Barcelona, pp 132–141

    Google Scholar 

  47. Maro R, Bai Y, Bahar RI (2000) Dynamically reconfiguring processor resources to reduce power consumption in high-performance processors. In: Proceedings of power aware computer systems (PACS) Workshop, held in conjunction with ASPLOS, Cambridge

    Google Scholar 

  48. McNairy C, Bhatia R (2005) Montecito: a dual-core, dual-thread Itanium Processor. IEEE Micro 25(2):10–20 (see also, Hot Chips 2004)

    Google Scholar 

  49. Oklobdzija VG (1998) Architectural tradeoffs for low power. In: Proceedings of the ISCA Workshop on Power-Driven Microarchitectures, Barcelona

    Google Scholar 

  50. Reed P et al (1997) 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller. Dig Tech Pap IEEE Int Solid St Circ Conf 40:412

    Google Scholar 

  51. Sakurai T, Newton R (1990) Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE JSSC 25(2):584–594

    Google Scholar 

  52. Sanchez H et al (1997) Thermal management system for high performance PowerPC microprocessors. In: Digest of papers, IEEE COMPCON, p 325

    Google Scholar 

  53. Seng JS, Tullsen DM, Cai G (2000) The power efficiency of multithreaded architectures. In: Invited talk presented at: ISCA Workshop on Complexity-Effective Design (WCED), Vancouver

    Google Scholar 

  54. Singhal R (2008) Inside intel core microarchitecture (Nehalem). Presented at Hot Chips-20, Stanford

    Google Scholar 

  55. Sohi G, Breach SE, Vijaykumar TN (1995) Multiscalar Processors. In: Proceedings of the 22nd annual international symposium on computer architecture, IEEE CS Press, Los Alamitos, pp 414–425

    Google Scholar 

  56. Srinivasan V, Brooks D, Gschwind M, Bose P, Zyuban V, Strenski PN, Emma PG (2002) Optimizing pipelines for power and performance. In: Proceedings of the 35th annual IEEE/ACM symposium on microarchitecture (MICRO-35), ACM/IEEE, Istanbul

    Google Scholar 

  57. Talks presented at the ISCA workshops on complexity effective design (WCED-2000 through WCED-2006), http://www.csl.cornell.edu/∼albonesi/wced.html

  58. Talks presented at the kool chips workshops (1998) http://www.cs.colorado.edu/∼grunwald/LowPowerWorkshop

  59. Talks presented at the power aware computer systems (PACS) Workshops; e.g. the 2004 offering: http://www.ece.cmu.edu/∼pacs04/

  60. Tendler JM, Dodson JS, Fields JS Jr, Le H, Sinharoy B (2002) POWER4 system microarchitecture. IBM J Res Dev 46:(1):1–116

    Google Scholar 

  61. The International Technology Roadmap for Semiconductors. http://www.itrs.net/reports.html

  62. Theme issue (1997) The future of processors. IEEE Comput 30(9):97–93

    Google Scholar 

  63. Tiwari V et al (1998) Reducing power in high-performance microprocessors. In: Proceedings of the IEEE/ACM Design Automation Conference. ACM, New York, pp 732–737

    Google Scholar 

  64. Tullsen DM, Eggers SJ, Levy HM (1995) Simultaneous Multithreading: Maximizing On-Chip parallelism. In: Proceedings of the 22nd annual internatonal symposium on computer architecture, Santa Margherita Ligure, pp 292–403

    Google Scholar 

  65. Yen D (2005) Chip multithreading processors enable reliable high throughput computing. Keynote speech at international symposium on reliability physics (IRPS)

    Google Scholar 

  66. Zyuban V (2000) Inherently lower-power high performance super scalar architectures. PhD thesis, Department of Computer Science and Engineering, University of Notre Dame

    Google Scholar 

  67. Papers in the special issue of IBM Journal of Research and Development, March/May 2002

    Google Scholar 

  68. Zyuban V, Brooks D, Srinivasan V, Gschwind M, Bose P, Strenski P, Emma P (2004) Integrated analysis of power and performance for pipelined microprocessors. IEEE T Comput 53(8):1004–1016

    Google Scholar 

  69. Zyuban V, Kogge P (2000) Optimization of high-performance superscalar architectures for energy efficiency. In: Proceedings of the IEEE symposium on low power electronics and design, ACM, New York

    Google Scholar 

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  1. Reliability & Power-Aware Microarchitectures, IBM Corp. T.J. Watson Research Center, P.O. Box 218, 1101 Kitchawan Road, 10598, Yorktown Heights, NY, USA

    Pradip Bose (Dr.)

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  1. Pradip Bose
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  1. University of Illinois at Urbana-Champaign, Urbana, IL, USA

    David Padua

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Bose, P. (2011). Power Wall. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_499

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