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VLIW Processors

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Definition

VLIW (Very Long Instruction Word) is a CPU architectural style that offers large amounts of irregular instruction-level parallelism (ILP) by overlapping the execution of multiple machine-level operations within a single flow of control. In a VLIW, the instruction-level parallelism is visible in the machine-level program and must be exposed and arranged before programs run; this complex job is done using sophisticated compiler technology, with little, if any, help from the programmer. A classic organization of a VLIW instruction consists of many individual operations bundled together into a long instruction word, with one such word issued each processor cycle. VLIW processors are used extensively in high-performance embedded applications, and have found some success as high-performance servers.

Discussion

VLIW architectures offer large amounts of instruction-level parallelism by arranging a parallel execution pattern in advance of the running of the program. The parallelism...

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Bibliography

  1. Fisher JA (1979) The optimization of horizontal microcode within and beyond basic blocks: an application of processor scheduling with resources. Ph.D. dissertation, Technical Report COO-3077–161. Courant Mathematics and Computing Laboratory, New York University, New York

    Google Scholar 

  2. Fisher JA (1981) Trace scheduling: a technique for global microcode compaction. IEEE T Comput 30(7):478–490

    Article  Google Scholar 

  3. Fisher JA (1983) Very long instruction word architectures and the ELI-512. In: Proceedings of the 10th annual international symposium on computer architecture, Stockholm, Sweden, 13–17 June 1983, pp 140–150

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  4. Charlesworth A (1981) An approach to scientific array processing: the architectural design of the AP-120b/FPS-164 family. IEEE Comput 14(3):18–27

    Article  MathSciNet  Google Scholar 

  5. Touzeau RF (1984) A FORTRAN compiler for the FPS-164 scientific computer. In: Proceedings of ACM SIGPLAN’ 84 symposium on compiler construction, Montreal, pp 48–57

    Chapter  Google Scholar 

  6. Rau BR, Glaeser CD (198) Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In: Proceedings of the 14th annual microprogramming workshop, IEEE Press, Piscataway, pp 183–197

    Google Scholar 

  7. Fisher JA, Faraboschi P, Young C (2005) Embedded computing – a VLIW approach to architecture, compiler, and tools. Morgan Kaufmann, San Francisco

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Fisher, J.A., Faraboschi, P., Young, C. (2011). VLIW Processors. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_471

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