Encyclopedia of Parallel Computing

2011 Edition
| Editors: David Padua

Trace Scheduling

  • Stefan M. Freudenberger
Reference work entry
DOI: https://doi.org/10.1007/978-0-387-09766-4_251


Trace scheduling is a global acyclic instruction scheduling technique in which the scheduling region consists of a linear acyclic sequence of basic blocks embedded in the control flow graph. Trace scheduling differs from other global acyclic scheduling techniques by allowing the scheduling region to be entered after the first instruction.

Trace scheduling was the first global instruction scheduling technique that was proposed and successfully implemented in both research and commercial compilers. By demonstrating that simple microcode operations could be statically compacted and scheduled on multi-issue hardware, trace scheduling provided the basis for making large amounts of instruction-level parallelism practical. Its first commercial implementation demonstrated that commercial codes could be statically compiled for multi-issue architectures, and thus greatly influenced and contributed to the performance of superscalar architectures. Today, the ideas of trace scheduling...

This is a preview of subscription content, log in to check access.


  1. 1.
    Aiken A, Nicolau A (1988) Optimal loop parallelization. In: Proceedings of the SIGPLAN 1988 conference on programming language design and implementation, June 1988, pp 308–317Google Scholar
  2. 2.
    Chang PP, Warter NJ, Mahlke SA, Chen WY, Hwu WW (1991) Three superblock scheduling models for superscalar and superpipelined processors. Technical Report CRHC-91-29. Center for Reliable and High-Performance Computing, University of Illinois at Urbana-ChampaignGoogle Scholar
  3. 3.
    Chang PP, Mahlke SA, Chen WY, Warter NJ, Hwu WW (1991) IMPACT: an architectural framework for multiple-instruction-issue processors. In: Proceedings of the 18th annual international symposium on computer architecture, May 1991, pp 266–275Google Scholar
  4. 4.
    Ellis JR (1985) Bulldog: a compiler for VLIW architectures. PhD thesis, Yale UniversityGoogle Scholar
  5. 5.
    Fisher JA (1993) Global code generation for instruction-level parallelism: trace scheduling-2. Technical Report HPL-93-43. Hewlett-Packard LaboratoriesGoogle Scholar
  6. 6.
    Fisher JA (1981) Trace scheduling: a technique for global microcode compaction, IEEE Trans Comput, July 1981, 30(7):478–490Google Scholar
  7. 7.
    Fisher JA (1979) The optimization of horizontal microcode within and beyond basic blocks. PhD dissertation. Technical Report COO-3077-161. Courant Institute of Mathematical Sciences, New York University, New York, NYGoogle Scholar
  8. 8.
    Freudenberger SM, Gross TR, Lowney PG (1994) Avoidance and suppression of compensation code in a trace scheduling compiler, ACM Trans Program Lang Syst, July 1994, 16(4):1156–1214Google Scholar
  9. 9.
    Havanki WA (1997) Treegion scheduling for VLIW processors. MS thesis. Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NCGoogle Scholar
  10. 10.
    Havanki WA, Banerjia S, Conte TM (1998) Treegion scheduling for wide issue processors. In: Proceedings of the fourth international symposium on high-performance computer architecture, February 1998, pp 266–276Google Scholar
  11. 11.
    Hwu WW, Mahlke SA, Chen WY, Chang PP, Warter NJ, Bringmann RA, Ouellette RG, Hank RE, Kiyohara T, Haab GE, Holm JG, Lavery DM (May 1993) The superblock: an effective technique for VLIW and superscalar compilation. J Supercomput, 7(1–2):229–248Google Scholar
  12. 12.
    Lowney PG, Freudenberger SM, Karzes TJ, Lichtenstein WD, Nix RP, O’Donnell JS, Ruttenberg JC (1993) The Multiflow trace scheduling compiler, J Supercomput, May 1993, 7(1-2):51–142Google Scholar
  13. 13.
    Mahlke SA, Lin DC, Chen WY, Hank RE, Bringmann RA (1992) Effective compiler support for predicated execution using the hyperblock. In: Proceedings of the 25th annual international symposium on microarchitecture, 1992, pp 45–54Google Scholar
  14. 14.
    Mahlke SA, Chen WY, Bringmann RA, Hank RE, Hwu WW, Rau BR, Schlansker MS (1993) Sentinel scheduling: a model for compiler-controlled speculative execution, ACM Trans Comput Syst, November 1993, 11(4):376–408Google Scholar
  15. 15.
    Moon SM, Ebcioglu K (1997) Parallelizing nonnumerical code with selective scheduling and software pipelining, ACM Trans Program Lang Syst, November 1997, 19(6):853–898Google Scholar
  16. 16.
    Zhou H, Conte TM (2002) Code size efficiency in global scheduling for ILP processors. In: Proceedings of the sixth annual workshop on the interaction between compilers and computer architectures, February 2002, pp 79–90Google Scholar
  17. 17.
    Zhou H, Jennings MD, Conte TM (2001) Tree traversal scheduling: a global scheduling technique for VLIW/EPIC processors. In: Proceedings of the 14th annual workshop on languages and compilers for parallel computing, August 2001, pp 223–238Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Stefan M. Freudenberger
    • 1
  1. 1.Freudenberger ConsultingFreudenberger ConsultingZürichSwitzerland