Synonyms
Definition
The memory wall describes implications of the processor/memory performance gap that has grown steadily over the last several decades. If memory latency and bandwidth become insufficient to provide processors with enough instructions and data to continue computation, processors will effectively always be stalled waiting on memory. The trend of placing more and more cores on chip exacerbates the situation, since each core enjoys a relatively narrower channel to shared memory resources. The problem is particularly acute in highly parallel systems, but occurs in platforms ranging from embedded systems to supercomputers, and is not limited to multiprocessors.
Discussion
Introduction
The term memory wall was coined in a short, controversial note that William A. Wulf and Sally A. McKee published in a 1995 issue of the ACM SIGArch Computer Architecture News (“Hitting the Memory Wall: Implications of the Obvious” [11]). At the time, most computer...
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Bibliography
Burger D, Goodman J, Kägi A (1996) Memory bandwidth limitations of future microprocessors. In: Proceedings of the 23rd International Symposium on Computer Architecture, Philadelphia, 22–24 May 1996. IEEE/ACM, Los Alamitos/New York, pp 78–89
Jacob B, Ng S, Wang D (2007) Memory systems: cache, DRAM, disk, 1st edn. Elsevier/Morgan Kaufmann, Burlington/San Francisco
Liu C, Sivasubramaniam A, Kandemir M (2004) Organizing the last line of defense before hitting the memory wall for CMPs. In: Proceedings of the 10th IEEE Symposium on High Performance Computer Architecture, Madrid, 14–18 Feb 2004. IEEE, Los Alamitos, pp 176–185
Murphy R (2007) On the effects of memory latency and bandwidth on supercomputer application performance. In: Proceedings of the IEEE International Symposium on Workload Characterization, Boston, 27–29 Sept 2007. IEEE, Piscataway, pp 35–43
Ousterhout J (1990) Why aren’t operating systems getting faster as fast as hardware? In: Proceedings of the Summer USENIX Technical Conference, June 1990, pp 247–256
Rogers B, Krishna A, Bell G, Vu K, Jiang X, Solihin Y (2009) Scaling the bandwidth wall: challenges in and avenues for CMP scaling. In: Proceedings of the 36th International Symposium on Computer Architecture, Austin, 20–24 June 2009. IEEE/ACM, Los Alamitos/New York, pp 371–382
Sites R (1996) It’s the memory, stupid. Microprocessor Rep 10(10):2–3
Srivastava S (2001) CEO interview. Wall Street Reporter, Aug 2001
Stokes J (2008) Analysis: more than 16 cores may well be pointless. In: Ars Technica. Condé Nast Digital. Available http://arstechnica.com/hardware/news/2008/12/analysis-more-than-16-cores-may-well-be-pointless.ars, Dec. 2008
Wilkes M (1995) The memory wall and the CMOS end-point. Comput Archit News 23(4):4–6
Wulf W, McKee S (1995) Hitting the memory wall: implications of the obvious. Comput Archit News 23(1):20–24
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this entry
Cite this entry
McKee, S.A., Wisniewski, R.W. (2011). Memory Wall. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_234
Download citation
DOI: https://doi.org/10.1007/978-0-387-09766-4_234
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-09765-7
Online ISBN: 978-0-387-09766-4
eBook Packages: Computer ScienceReference Module Computer Science and Engineering