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Hybrid Optimization Techniques for System-Level Design Space Exploration

  • Michael GlaßEmail author
  • Jürgen Teich
  • Martin Lukasiewycz
  • Felix Reimann
Reference work entry

Abstract

Embedded system design requires to solve synthesis steps that consist of resource allocation, task binding, data routing, and scheduling. These synthesis steps typically occur several times throughout the entire design cycle and necessitate similar concepts even at different levels of abstraction. In order to cope with the large design space, fully automatic Design Space Exploration (DSE) techniques might be applied. In practice, the high complexity of these synthesis steps requires efficient approaches that also perform well in the presence of stringent design constraints. Those constraints may render vast areas in the search space infeasible with only a fraction of feasible implementations that are sparsely distributed. This is a serious problem for metaheuristics that are popular for DSE of electronic hardware/software systems, since they are faced with large areas of infeasible implementations where no gradual improvement is possible. In this chapter, we present an approach that combines metaheuristic optimization with search algorithms to solve the problem of Hardware/Software Codesign (HSCD) including allocation, binding, and scheduling. This hybrid optimization uses powerful search algorithms to determine feasible implementations This avoids an exploration of infeasible areas and, thus, enables a gradual improvement as required for efficient metaheuristic optimization. Two methods are presented that can be applied to both, problems with linear as well as non-linear constraints, the latter being particularly intended to address aspects such as timeliness or reliability which cannot be approximated by linear constraints in a sound fashion. The chapter is concluded with several examples for a successful use of the introduced techniques in different application domains.

Acronyms

BIST

Built-In Self-Test

DPLL

Davis-Putnam-Logemann-Loveland

DSE

Design Space Exploration

EA

Evolutionary Algorithm

E/E

Electric and Electronic

ESL

Electronic System Level

HSCD

Hardware/Software Codesign

ILP

Integer Linear Program

MoC

Model of Computation

MPSoC

Multi-Processor System-on-Chip

PB

Pseudo-Boolean

SAT

Boolean Satisfiability

SMT

Satisfiability Modulo Theories

References

  1. 1.
    Blickle T, Teich J, Thiele L (1998) System-level synthesis using evolutionary algorithms. Des Autom Embed Syst 3(1):23–58CrossRefGoogle Scholar
  2. 2.
    Coello Coello CA (2002) Theoretical and numerical constraint-handling techniques used with evolutionary algorithms: a survey of the state of the art. Comput Methods Appl Mech Eng 191(11–12):1245–1287MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Davis M, Logemann G, Loveland D (1962) A machine program for theorem-proving. Commun ACM 5(7):394–397MathSciNetCrossRefzbMATHGoogle Scholar
  4. 4.
    De Moura L, Bjørner N (2011) Satisfiability modulo theories: introduction and applications. Commun ACM 54(9):69–77CrossRefGoogle Scholar
  5. 5.
    Gajski DD, Kuhn RH (1983) New VLSI tools. IEEE Comput 16(12):11–14CrossRefGoogle Scholar
  6. 6.
    Gerstlauer A, Haubelt C, Pimentel A, Stefanov T, Gajski D, Teich J (2009) Electronic system-level synthesis methodologies. IEEE Trans Comput Aided Des Integr Circuits Syst 28(10):1517–1530CrossRefGoogle Scholar
  7. 7.
    Glaß M, Lukasiewycz M, Reimann F, Haubelt C, Teich J (2010) Symbolic system level reliability analysis. In: Proceedings of the international conference on computer-aided design (ICCAD), San Jose, pp 185–189Google Scholar
  8. 8.
    Graf S, Glaß M, Teich J, Lauer C (2014) Multi-variant-based design space exploration for automotive embedded systems. In: Proceedings of design, automation and test in Europe (DATE), p 6Google Scholar
  9. 9.
    Graf S, Glaß M, Wintermann D, Teich J, Lauer C (2013) IVaM: implicit variant modeling and management for automotive embedded systems. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES+ISSS), p 10Google Scholar
  10. 10.
    Graf S, Reimann F, Glaß M, Teich J (2014) Towards scalable symbolic routing for multi-objective networked embedded system design and optimization. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp 2:1–2:10Google Scholar
  11. 11.
    Hernandez-Aguirre A, Botello-Rionda S, Coello Coello CA, Lizarraga-Lizarraga G, Mezura-Montes E (2004) Handling constraints using multiobjective optimization concepts. Int J Numer Methods Eng 59(15):1989–2017MathSciNetCrossRefzbMATHGoogle Scholar
  12. 12.
    Kienhuis ACJ (1999) Design space exploration of stream-based dataflow architectures – methods and tools. Ph.D. thesis, Delft University of TechnologyGoogle Scholar
  13. 13.
    Le Berre D, Parrain A (2010) The Sat4J library, release 2.2. system description. J Satisf Boolean Model Comput 7:59–64Google Scholar
  14. 14.
    Lukasiewycz M, Chakraborty S (2012) Concurrent architecture and schedule optimization of time-triggered automotive systems. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp 383–392Google Scholar
  15. 15.
    Lukasiewycz M, Glaß M, Haubelt C, Teich J (2007) Solving multiobjective Pseudo-Boolean problems. In: Proceedings of the international conference on theory and applications of satisfiability testing (SAT), pp 56–69Google Scholar
  16. 16.
    Lukasiewycz M, Glaß M, Haubelt C, Teich J (2008) Efficient symbolic multi–objective design space exploration. In: Proceedings of the Asia and South Pacific design automation conference (ASPDAC), Seoul, pp 691–696Google Scholar
  17. 17.
    Lukasiewycz M, Glaß M, Haubelt C, Teich J, Regler R, Lang B (2008) Concurrent topology and routing optimization in automotive network integration. In: Proceedings of the design automation conference (DAC), Anaheim, pp 626–629Google Scholar
  18. 18.
    Lukasiewycz M, Glaß M, Reimann F Opt4J–meta-heuristic optimization framework for java. http://www.opt4j.org/
  19. 19.
    Lukasiewycz M, Glaß M, Reimann F, Teich J (2011) Opt4J: a modular framework for meta-heuristic optimization. In: Proceedings of the genetic and evolutionary computation conference (GECCO), pp 1723–1730Google Scholar
  20. 20.
    Lukasiewycz M, Reimann F OpenDSE–open design space exploration framework. http://opendse.sourceforge.net/
  21. 21.
    Lukasiewycz M, Streubühr M, Glaß M, Haubelt C, Teich J (2009) Combined system synthesis and communication architecture exploration for MPSoCs. In: Proceedings of design, automation and test in Europe (DATE), pp 472–477Google Scholar
  22. 22.
    Prakash S, Parker AC (1992) SOS: synthesis of application-specific heterogeneous multiprocessor systems. J Parallel Distrib Comput 16(4):338–351CrossRefzbMATHGoogle Scholar
  23. 23.
    Puchinger J, Raidl G (2005) Combining metaheuristics and exact algorithms in combinatorial optimization: a survey and classification. In: Proceedings of the first international work-conference on the interplay between natural and artificial computation (IWINAC), vol 3562, pp 41–53Google Scholar
  24. 24.
    Reimann F, Glaß M, Haubelt C, Eberl M, Teich J (2010) Improving platform-based system synthesis by satisfiability modulo theories solving. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp 135–144Google Scholar
  25. 25.
    Reimann F, Glaß M, Teich J, Cook A, Gómez LR, Ull D, Wunderlich HJ, Abelein U, Engelke P (2014) Advanced diagnosis: SBST and BIST integration in automotive E/E architectures. In: Proceedings of the design automation conference (DAC), p 8Google Scholar
  26. 26.
    Reimann F, Lukasiewycz M, Glaß M, Haubelt C, Teich J (2011) Symbolic system synthesis in the presence of stringent real-time constraints. In: Proceedings of the design automation conference (DAC), pp 393–398Google Scholar
  27. 27.
    Smith AE, Coit DW (1997) Penalty functions, chap. C 5.2. Institute of Physics Publishing and Oxford University Press, BristolGoogle Scholar
  28. 28.
    Teich J (2012) Hardware/software co-design: past, present, and predicting the future. Proc IEEE 100(5):1411–1430CrossRefGoogle Scholar
  29. 29.
    Teich J, Blickle T, Thiele L (1997) An evolutionary approach to system-level synthesis. In: Proceedings of the international workshop on hardware/software codesign (CODES/CASHE), pp 167–171Google Scholar
  30. 30.
    Teich J, Haubelt C (2007) Digitale hardware/software-systeme: synthese und optimierung, 2nd edn. Springer, HeidelbergzbMATHGoogle Scholar
  31. 31.
    Weichslgartner A, Gangadharan D, Wildermann S, Glaß M, Teich J (2014) DAARM: design-time application analysis and run-time mapping for predictable execution in many-core systems. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp 34:1–34:10Google Scholar
  32. 32.
    Zitzler E, Thiele L (1999) Multiobjective evolutionary algorithms: a comparative case study and the strength Pareto approach. IEEE Trans Evol Comput 3(4):257–271CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2017

Authors and Affiliations

  • Michael Glaß
    • 1
    Email author
  • Jürgen Teich
    • 2
  • Martin Lukasiewycz
    • 3
  • Felix Reimann
    • 4
  1. 1.Institute of Embedded Systems/Real-Time Systems at Ulm UniversityUlmGermany
  2. 2.Department of Computer ScienceFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)ErlangenGermany
  3. 3.Robert Bosch GmbH, Corporate ResearchRenningenGermany
  4. 4.Audi Electronics Venture GmbHGaimersheimGermany

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