Encyclopedia of Big Data Technologies

2019 Edition
| Editors: Sherif Sakr, Albert Y. Zomaya

Computer Architecture for Big Data

  • Behrooz ParhamiEmail author
Reference work entry
DOI: https://doi.org/10.1007/978-3-319-77525-8_164



How features of general-purpose computer architecture impact big-data applications and, conversely, how requirements of big data lead to the emergence of new hardware and architectural support.


Computer architecture (Parhami 2005) is a subdiscipline of computer science and engineering that is concerned with designing computing structures to meet application requirements effectively, economically, reliably, and within prevailing technological constraints. In this entry, we discuss how features of general-purpose computer architecture impacts big-data applications and, conversely, how requirements of big data lead to the emergence of new hardware and architectural support.

Historical Trends in Computer Architecture

The von Neumann architecture for stored-program computers, with its single or unified memory, sometimes referred to as the Princeton architecture, emerged in 1945 (von Neumann 1945...

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  1. Aiken HH, Hopper GM (1946) The automatic sequence controlled calculator – I. Electr Eng 65(8–9):384–391MathSciNetzbMATHCrossRefGoogle Scholar
  2. Bandi N, Sun C, Agrawal D, El Abbadi A (2004) Hardware acceleration in commercial databases: a case study of spatial operations. In: Proceedings of the international conference on very large data bases, Toronto, pp 1021–1032Google Scholar
  3. Baraniuk R (2007) Compressive sensing. IEEE Signal Process Mag 24(4):118–121CrossRefGoogle Scholar
  4. Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Comput 35(1):70–78CrossRefGoogle Scholar
  5. Bossuet L, Grand M, Gaspar L, Fischer V, Gogniat G (2013) Architectures of flexible symmetric key crypto engines – a survey: from hardware coprocessor to multi-crypto-processor system on chip. ACM Comput Surv 45(4):41CrossRefGoogle Scholar
  6. Casper J, Olukotun K (2014) Hardware acceleration of database operations. In: Proceedings of ACM/SIGDA international symposium on field-programmable gate arrays, Monterey, CA, pp 151–160Google Scholar
  7. Cattell R (2011) Scalable SQL and NoSQL data stores. ACM SIGMOD Rec 39(4):12–27CrossRefGoogle Scholar
  8. Caulfield AM et al (2016) A cloud-scale acceleration architecture. In: Proceedings of 49th IEEE/ACM international symposium on microarchitecture, Orlando, FL, pp 1–13Google Scholar
  9. Ceze L, Hill MD, Wenisch TE (2016) Arch2030: a vision of computer architecture research over the next 15 years, Computing Community Consortium. http://cra.org/ccc/wp-content/uploads/sites/2/2016/12/15447-CCC-ARCH-2030-report-v3-1-1.pdf
  10. Chen JX (2016) The evolution of computing: AlphaGo. Comput Sci Eng 18(4):4–7CrossRefGoogle Scholar
  11. Chen CLP, Zhang C-Y (2014) Data-intensive applications, challenges, techniques and technologies: a survey on big data. Inf Sci 275:314–347CrossRefGoogle Scholar
  12. Cyrluk D, Rajan S, Shankar N, Srivas MK (1995) Effective theorem proving for hardware verification. In: Theorem provers in circuit design. Springer, Berlin, pp 203–222CrossRefGoogle Scholar
  13. Danowitz A, Kelley K, Mao J, Stevenson JP, Horowitz M (2012) CPU DB: recording microprocessor history. Commun ACM 55(4):55–63CrossRefGoogle Scholar
  14. Eggers SJ, Emer JS, Levy HM, Lo JL, Stamm RL, Tullsen DM (1997) Simultaneous multithreading: a platform for next-generation processors. IEEE Micro 17(5):12–19CrossRefGoogle Scholar
  15. Gepner P, Kowalik MF (2006) Multi-core processors: new way to achieve high system performance. In: Proceedings of IEEE international symposium on parallel computing in electrical engineering, Bialystok, pp 9–13Google Scholar
  16. Govindaraju NK, Lloyd B, Wang W, Lin M, Manocha D (2004) Fast computation of database operations using graphics processors. In: Proceedings of the ACM SIGMOD international conference on management of data, Paris, pp 215–226Google Scholar
  17. Hall SH, Hall GW, McCall JA (2000) High-speed digital system design: a handbook of interconnect theory and design practices. Wiley, New YorkGoogle Scholar
  18. Herlihy M, Moss JEB (1993) Transactional memory: architectural support for lock-free data structures. In: Proceedings of the international symposium on computer architecture, San Diego, CA, pp 289–300Google Scholar
  19. Hilbert M, Lopez P (2011) The world’s technological capacity to store, communicate, and compute information. Science 332:60–65CrossRefGoogle Scholar
  20. Hu H, Wen Y, Chua T-S, Li X (2014) Toward scalable systems for big data analytics: a technology tutorial. IEEE Access 2:652–687CrossRefGoogle Scholar
  21. Kuon I, Tessier R, Rose J (2008) FPGA architecture: survey and challenges. Found Trends Electron Des Autom 2(2):135–253CrossRefGoogle Scholar
  22. Le Gall D (1991) MPEG: a video compression standard for multimedia applications. Commun ACM 34(4):46–58CrossRefGoogle Scholar
  23. Lee RB (1995) Accelerating multimedia with enhanced microprocessors. IEEE Micro 15(2):22–32CrossRefGoogle Scholar
  24. Lee J, Kim H, Yoo S, Choi K, Hofstee HP, Nam GJ, Nutter MR, Jamsek D (2017) ExtraV: boosting graph processing near storage with a coherent accelerator. Proc VLDB Endowment 10(12):1706–1717CrossRefGoogle Scholar
  25. Liu AX, Meiners CR, Torng E (2010) TCAM razor: a systematic approach towards minimizing packet classifiers in TCAMs. IEEE/ACM Trans Networking 18(2):490–500CrossRefGoogle Scholar
  26. Markgraf JD (2007) The von Neumann Bottleneck. On-line source that is no longer accessible (will find a replacement for this reference during revisions)Google Scholar
  27. McKee SA (2004) Reflections on the memory wall. In: Proceedings of the conference on computing frontiers, Ischia, pp 162–167Google Scholar
  28. Mueller R, Teubner J, Alonso G (2012) Sorting networks on FPGAs. Int J Very Large Data Bases 21(1):1–23CrossRefGoogle Scholar
  29. Nvidia (2016) Nvidia Tesla P100: infinite compute power for the modern data center – technical overview. On-line document. http://images.nvidia.com/content/tesla/pdf/nvidia-teslap100-techoverview.pdf. Accessed 18 Feb 2018
  30. Owens JD et al (2008) GPU computing. Proc IEEE 96(5):879–899CrossRefGoogle Scholar
  31. Parhami B (1999) Chapter 7: Sorting networks. In: Introduction to parallel processing: algorithms and architectures. Plenum Press, New York, pp 129–147Google Scholar
  32. Parhami B (2005) Computer architecture: from microprocessors to supercomputers. Oxford University Press, New YorkGoogle Scholar
  33. Pirsch P, Demassieux N, Gehrke W (1995) VLSI architectures for video compression – a survey. Proc IEEE 83(2):220–246CrossRefGoogle Scholar
  34. Rau BR, Fisher JA (1993) Instruction-level parallel processing: history, overview, and perspective. J Supercomput 7(1–2):9–50CrossRefGoogle Scholar
  35. Rixner S (2001) Stream processor architecture. Kluwer, BostonzbMATHGoogle Scholar
  36. Sato K, Young C, Patterson D (2017) An in-depth look at Google’s first tensor processing unit, google cloud big data and machine learning blog, May 12. On-line document. http://cloud.google.com/blog/big-data/2017/05/an-in-depth-look-at-googles-first-tensor-processing-unit-tpu. Accessed 18 Feb 2018
  37. Scott ND, Olsen DM, Gannett EW (1998) An overview of the visualize FX graphic accelerator hardware. Hewlett Packard J 49:28–29Google Scholar
  38. Shafer J, Rixner S, Cox AL (2010) The Hadoop distributed filesystem: balancing portability and performance. In: Proceedings of the IEEE international symposium on performance analysis of systems & software, White Plains, NY, pp 122–133Google Scholar
  39. Shaw DE (1982) The non-von supercomputer, Columbia University technical report, on-line document. http://academiccommons.columbia.edu/catalog/ac:140914. Accessed 18 Feb 2018
  40. Singer G (2013) The history of the modern graphics processor, TechSpot on-line article. http://www.techspot.com/article/650-history-of-the-gpu/. Accessed 18 Feb 2018
  41. Sklyarov V et al (2015) Hardware accelerators for information retrieval and data mining. In: Proceedings of the IEEE conference on information and communication technology research, Bali, pp 202–205Google Scholar
  42. Smith AJ (1982) Cache memories. ACM Comput Surv 14(8):473–530CrossRefGoogle Scholar
  43. Smotherman M (2010) IBM stretch (7030) – aggressive uniprocessor parallelism. On-line document. http://people.cs.clemson.edu/~mark/stretch.html. Accessed 18 Feb 2018
  44. Stanford University (2012) 21st century computer architecture: a community white paper, on-line document. http://csl.stanford.edu/~christos/publications/2012.21stcenturyarchitecture.whitepaper.pdf. Accessed 18 Feb 2018
  45. Storer J (1988) Data compression. Computer Science Press, RockvilleGoogle Scholar
  46. Taylor DE (2005) Survey and taxonomy of packet classification techniques. ACM Comput Surv 37(3):238–275CrossRefGoogle Scholar
  47. von Neumann J (1945) First draft of a report on the EDVAC, University of Pennsylvania. On-line document. http://web.archive.org/web/20130314123032/http://qss.stanford.edu/~godfrey/vonNeumann/vnedvac.pdf. Accessed 14 Feb 2018
  48. von Neumann J, Burks AW, Goldstine HH (1947) Preliminary discussion of the logical design of an electronic computing instrument. Institute for Advanced Study, PrincetonGoogle Scholar
  49. Ward MO, Grinstein G, Keim D (2010) Interactive data visualization: foundations, techniques, and applications. CRC Press, NatickzbMATHGoogle Scholar
  50. Wulf W, McKee S (1995) Hitting the wall: implications of the obvious. ACM Comput Archit News 23(1):20–24CrossRefGoogle Scholar
  51. Yoon C-W, Woo R, Kook J, Lee S-J, Lee K, Yoo H-J (2001) An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator, and 3-D rendering engine for mobile applications. IEEE J Solid State Circuits 36(11):1758–1767CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of CaliforniaSanta BarbaraUSA

Section editors and affiliations

  • Bingsheng He
  • Behrooz Parhami
    • 1
  1. 1.Dept. of Electrical and Computer EngineeringUniversity of California, Santa BarbaraSanta BarbaraUSA