Machine Vision Handbook pp 1103-1136 | Cite as
Implementing Machine Vision Systems Using FPGAs
Abstract
Field programmable gate arrays (FPGAs) offer a convenient and flexible platform on which real-time machine vision systems may be implemented. This chapter discusses how FPGA based design differs from conventional software design for implementing image processing algorithms. Simply porting from software to hardware can give disappointing results. The process of transforming an algorithm for mapping it onto an FPGA is described in some detail, illustrating how a range of low-level image processing operations may be efficiently implemented. Systems integration issues such as interfacing, debugging and tuning are also discussed.
Keywords
Clock Cycle Field Programmable Gate Array Machine Vision System Hardware Description Language Frame BufferNotes
Acknowledgements
I would like to acknowledge my research students (David Johnson, Kim Gribbon, Chris Johnston, Aaron Bishell, Andreas Buhler, and Ni Ma) who helped shape my thinking as we struggled together to work out efficient ways of implementing image processing algorithms.
References
- 1.AIA (2004) Camera link specifications, vol 1.1. Automated Imaging Association, Ann Arbor, MIGoogle Scholar
- 2.Akeila H, Morris J (2008) High resolution stereo in real time. In: Robot vision, Auckland, New Zealand, 18–20 Feb 2008. Lecture notes in computer science, vol 4931, Springer-Verlag, Berlin, pp 72–84. doi:10.1007/978-3-540-78157-8_6Google Scholar
- 3.Alston I, Madahar B (2002) From C to netlists: hardware engineering for software engineers? IEE Electron Commun Eng J 14(4):165–173. doi:10.1049/ecej:20020404CrossRefGoogle Scholar
- 4.Altera (2010) Cyclone IV device handbook, vol CYIV-5 V1-1.1. Altera Corporation, San Jose, CAGoogle Scholar
- 5.Altera (2010) Stratix IV device handbook, vol SIV5V1-4.0. Altera Corporation, San Jose, CAGoogle Scholar
- 6.Amdahl GM (1967) Validity of the single processor approach to achieving large scale computing capabilities. In: AFIPS spring joint computer conference, Atlantic City, 18–20 April 1967, vol 30. ACM, New York, pp 483–485. doi:10.1145/1465482.1465560Google Scholar
- 7.Appiah K, Hunter A, Dickenson P, Owens J (2008) A run-length based connected component algorithm for FPGA implementation. In: International conference on field programmable technology, Taipei, 7–10 Dec 2008, pp 177–184. doi:10.1109/FPT.2008.4762381Google Scholar
- 8.Bailey DG (2011) Image border management for FPGA based filters. In: 6th IEEE international symposium on electronic design, test and applications, Queenstown, 17–19 Jan 2011, pp 144–149. doi:10.1109/DELTA.2011.34Google Scholar
- 9.Bailey DG (1988) Machine vision: a multi-disciplinary systems engineering problem. In: Hybrid image and signal processing, Orlando, 7–8 April 1988, vol SPIE 939, pp 148–155Google Scholar
- 10.Bailey DG (1991) Raster based region growing. In: 6th New Zealand image processing workshop, Lower Hutt, 29–30 August 1991, pp 21–26Google Scholar
- 11.Bailey DG, Bouganis CS (2009) Implementation of a foveal vision mapping. In: International conference on field programmable technology (FPT'09), Sydney, 9–11 Dec 2009, pp 22–29. doi:10.1109/FPT.2009.5377646Google Scholar
- 12.Bailey DG, Johnston CT (2010) Algorithm transformation for FPGA implementation. In: 5th IEEE international symposium on electronic design, test and applications (DELTA 2010), Ho Chi Minh City, 13–15 Jan 2010, pp 77–81. doi:10.1109/DELTA.2010.17Google Scholar
- 13.Bailey DG, Johnston CT (2007) Single pass connected components analysis. In: Image and vision computing New Zealand (IVCNZ), Hamilton, 5–7 Dec 2007, pp 282–287Google Scholar
- 14.Bailey DG, Johnston CT, Ma N (2008) Connected components analysis of streamed images. In: International conference on field programmable logic and applications (FPL 2008), Heidelberg, 8–10 Sep 2008, pp 679–682. doi:10.1109/FPL.2008.4630038Google Scholar
- 15.Buhler A (2007) GateOS: a minimalist windowing environment and operating system for FPGAs. Master of Engineering Thesis, Institute of Information Sciences and Technology, Massey University. hdl:10179/667Google Scholar
- 16.Catmull E, Smith AR (1980) 3-D transformations of images in scanline order. ACM SIGGRAPH Comput Graph 14(3):279–285. doi:10.1145/965105.807505CrossRefGoogle Scholar
- 17.DDWG (1999) Digital visual interface (DVI), vol 1.0. Digital Display Working Group, Vancouver, WAGoogle Scholar
- 18.Downton A, Crookes D (1998) Parallel architectures for image processing. IEE Electron Commun Eng J 10(3):139–151. doi:10.1049/ecej:19980307CrossRefGoogle Scholar
- 19.Edwards SA (2006) The challenges of synthesizing hardware from C-like languages. IEEE Des Test Comput 23(5):375–383. doi:10.1109/MDT.2006.134CrossRefGoogle Scholar
- 20.Gribbon KT, Bailey DG (2004) A novel approach to real time bilinear interpolation. In: 2nd IEEE international workshop on electronic design, test, and applications (DELTA 2004), Perth, 28–30 Jan 2004, pp 126–131. doi:10.1109/DELTA.2004.10055Google Scholar
- 21.Gribbon KT, Bailey DG, Bainbridge-Smith A (2007) Development issues in using FPGAs for image processing. In: Image and Vision Computing New Zealand (IVCNZ), Hamilton, 5–7 Dec 2007, pp 217–222Google Scholar
- 22.Gribbon KT, Johnston CT, Bailey DG (2003) A real-time FPGA implementation of a barrel distortion correction algorithm with bilinear interpolation. In: Image and Vision Computing New Zealand (IVCNZ'03), Palmerston North, 26–28 Nov 2003, pp 408–413Google Scholar
- 23.Herbordt MC, VanCourt T, Gu Y, Sukhwani B, Conti A, Model J, DiSabello D (2007) Achieving high performance with FPGA-based computing. IEEE Comput 40(3):50–57. doi:10.1109/MC.2007.79CrossRefGoogle Scholar
- 24.Hsia SC (2004) Fast high-quality color-filter-array interpolation method for digital camera systems. J Electron Imaging 13(1):244–247. doi:10.1117/1.1631443MathSciNetCrossRefGoogle Scholar
- 25.Hutton M, Schleicher J, Lewis D, Pedersen B, Yuan R, Kaptanoglu S, Baeckler G, Ratchev B, Padalia K, Bourgeault M, Lee A, Kim H, Saini R (2004) Improving FPGA performance and area using an adaptive logic module. In: 14th international conference on field programmable logic and applications, Antwerp, 29 Aug–1 Sep 2004. Lecture notes in computer science, vol 3203. Springer-Verlag, Berlin, pp 135–144. doi:10.1007/b99787Google Scholar
- 26.Johnston CT, Bailey DG (2008) FPGA implementation of a single pass connected components algorithm. In: IEEE international symposium on electronic design, test and applications (DELTA 2008), Hong Kong, 23–25 Jan 2008, pp 228–231. doi:10.1109/DELTA.2008.21Google Scholar
- 27.Kehtarnavaz N, Gamadia M (2006) Real-time image and video processing: from research to reality. In: Synthesis lectures on image, video and multimedia processing. Morgan & Claypool, San Rafael, CA. doi:10.2200/S00021ED1V01Y200604IVM005Google Scholar
- 28.Ma N, Bailey D, Johnston C (2008) Optimised single pass connected components analysis. In: International conference on field programmable technology, Taipei, 8–10 Dec 2008, pp 185–192. doi:10.1109/FPT.2008.4762382Google Scholar
- 29.McCollum AJ, Bowman CC, Daniels PA, Batchelor BG (1988) A histogram modification unit for real-time image enhancement. Comput Vis Graph Image Process 42(3):387–398. doi:10.1016/S0734-189X(88)80047-1CrossRefGoogle Scholar
- 30.Mentor (2010) Handel-C language reference manual, release v5.3_2. Mentor Graphics Corporation, Wilsonville, ORGoogle Scholar
- 31.Page I (1996) Closing the gap between hardware and software: hardware-software cosynthesis at Oxford. In: IEE colloquium on hardware-software cosynthesis for reconfigurable systems (Digest No: 1996/036), Bristol, 22 February 1996, pp 2/1–2/11. doi:10.1049/ic:19960221Google Scholar
- 32.Ridler TW, Calvard S (1978) Picture thresholding using an iterative selection method. IEEE Trans Syst Man Cybernet 8(8):630–632. doi:10.1109/TSMC.1978.4310039CrossRefGoogle Scholar
- 33.Rosenfeld A, Pfaltz J (1966) Sequential operations in digital picture processing. J Assoc Comput Machinery 13(4):471–494. doi:10.1145/321356.321357MATHCrossRefGoogle Scholar
- 34.Schaffer G (1984) Machine vision: a sense for computer integrated manufacturing. Am Mach 128(6):101–129Google Scholar
- 35.Schulte MJ, Stine JE (1997) Symmetric bipartite tables for accurate function approximation. In: 13th IEEE symposium on computer arithmetic, Asilomar, 6–9 July 1997, pp 175–183. doi:10.1109/ARITH.1997.614893Google Scholar
- 36.Waltz FM (1994) Separated-kernel image processing using finite-state machines (SKIPSM). In: Machine vision applications, architectures, and systems integration III, Boston, 31 Oct–2 Nov 1994, vol SPIE 2347, pp 386–395. doi:10.1117/12.188749Google Scholar
- 37.Waltz FM, Garnaoui HH (1994) Application of SKIPSM to binary morphology. In: Machine vision applications, architectures, and systems integration III, Boston, 31 Oct–2 Nov 1994, vol SPIE 2347, pp 396–407. doi:10.1117/12.188750Google Scholar
- 38.Wolberg G (1990) Digital image warping. IEEE Computer Society Press, Los Alamitos, CAGoogle Scholar
- 39.Wolberg G, Sueyllam HM, Ismail MA, Ahmed KM (2000) One-dimensional resampling with inverse and forward mapping functions. J Graph Tools 5:11–33Google Scholar
- 40.Xilinx (2009) Spartan-6 family overview, vol DS160 (v1.0). Xilinx Inc, San Jose, CAGoogle Scholar
- 41.Xilinx (2010) Spartan-6 FPGA CLB user guide, vol UG384 (v1.1). Xilinx Inc, San Jose, CAGoogle Scholar
- 42.Xilinx (2010) Virtex-6 family overview, vol DS150 (v2.2). Xilinx Inc, San Jose, CAGoogle Scholar