Encyclopedia of Algorithms

2016 Edition
| Editors: Ming-Yang Kao

Layout Decomposition for Triple Patterning

  • Bei Yu
  • David Z. PanEmail author
Reference work entry
DOI: https://doi.org/10.1007/978-1-4939-2864-4_744

Years and Authors of Summarized Original Work

  • 2011; Yu, Yuan, Zhang, Ding, Pan

Problem Definition

Layout decomposition is a key stage in triple patterning lithography manufacturing process, where the original designed layout is divided into three masks. There will be three exposure/etching steps, through which the circuit layout can be produced. When the distance between two input features is less than certain minimum distance min s, they need to be assigned to different masks (colors) to avoid coloring conflict. Sometimes coloring conflict can be resolved by splitting a pattern into two different masks. However, this introduces stitches, which lead to yield loss because of overlay error. Therefore, two of the main objectives in layout decomposition are conflict minimization and stitch minimization. An example of triple patterning layout decomposition is shown in Fig. 1, where all features are divided into three masks without any conflict and one stitch is introduced.

Keywords

Graph coloring Layout decomposition Lithography Mathematical programming 
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Recommended Reading

  1. 1.
    Fang SY, Chen WY, Chang YW (2012) A novel layout decomposition algorithm for triple patterning lithography. In: IEEE/ACM design automation conference (DAC), San Francisco, pp 1185–1190Google Scholar
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    Kuang J, Young EF (2013) An efficient layout decomposition approach for triple patterning lithography. In: IEEE/ACM design automation conference (DAC), Austin, pp 69:1–69:6Google Scholar
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    Tian H, Zhang H, Ma Q, Xiao Z, Wong M (2012) A polynomial time triple patterning algorithm for cell based row-structure layout. In: IEEE/ACM international conference on computer-aided design (ICCAD), San Jose, pp 57–64Google Scholar
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    Yu B, Pan DZ (2014) Layout decomposition for quadruple patterning lithography and beyond. In: IEEE/ACM design automation conference (DAC), San FranciscoGoogle Scholar
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    Yu B, Yuan K, Zhang B, Ding D, Pan DZ (2011) Layout decomposition for triple patterning lithography. In: IEEE/ACM international conference on computer-aided design (ICCAD), San Jose, pp 1–8Google Scholar
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    Yu B, Lin YH, Luk-Pat G, Ding D, Lucas K, Pan DZ (2013) A high-performance triple patterning layout decomposer with balanced density. In: IEEE/ACM International conference on computer-aided design (ICCAD), San Jose, pp 163–169Google Scholar
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    Yu B, Xu X, Gao JR, Pan DZ (2013) Methodology for standard cell compliance and detailed placement for triple patterning lithography. In: IEEE/ACM international conference on computer-aided design (ICCAD), San Jose, pp 349–356Google Scholar
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    Zhang Y, Luk WS, Zhou H, Yan C, Zeng X (2013) Layout decomposition with pairwise coloring for multiple patterning lithography. In: IEEE/ACM international conference on computer-aided design (ICCAD), San Jose, pp 170–177Google Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Department of Electrical and Computer Engineering, University of TexasAustinUSA