Encyclopedia of Algorithms

2008 Edition
| Editors: Ming-Yang Kao

Gate Sizing

2002; Sundararajan, Sapatnekar, Parhi
  • Vijay Sundararajan
Reference work entry
DOI: https://doi.org/10.1007/978-0-387-30162-4_159

Keywords and Synonyms

Fast and exact transistor sizing          

Problem Definition

Table 1

Comparison of TILOS and MINFLOTRANSIT on a Sun Ultrasparc 10 workstation for ISCAS85 and MCNC91 benchmarks for 0.13 um technology. The delay specs. are with respect to a minimum-sized circuit. The optimization approach followed here was gate sizing

Circuit

# Gates

Area Saved over TILOS

Delay Specs.

CPU TIME (TILOS)

CPU TIME (OURS)

         

Adder32

480

≤ 1%

0.5 Dmin

2.2 s

5 s

         

Adder256

3840

≤ 1%

0.5 Dmin

262 s

608 s

         

Cm163a

65

2.1%

0.55 Dmin

0.13 s

0.32 s

         

Cm162a

71

10.4%

0.5 Dmin

0.23 s

0.96 s

         

Parity8

89

37%

0.45 Dmin

0.68 s

2.15 s

         

Frg1

177

1.9%

0.7 Dmin

0.55 s

1.49 s

         

population

518

6.7%

0.4 Dmin

57 s

179 s

         

Pmult8

1431

5%

0.5 Dmin

637 s

1476 s

         

Alu2

826

2.6%

0.6 Dmin

28 s

71 s

         

C432

160

9.4%

0.4 Dmin

0.5 s

4.8 s

         

C499

202

7.2%

0.57 Dmin

1.47 s

11.26 s

         

C880

383

4%

0.4 Dmin

2.7 s

8,2 s

         

Keywords

Greedy Algorithm Steiner Tree Combinatorial Auction Submodular Function Social Surplus 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Recommended Reading

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Copyright information

© Springer-Verlag 2008

Authors and Affiliations

  • Vijay Sundararajan
    • 1
  1. 1.Texas InstrumentsDallasUSA