Skip to main content
SpringerLink
Log in

Introduction to Hardware/Software Codesign

  • Reference work entry
  • First Online:
Handbook of Hardware/Software Codesign

Abstract

Hardware/Software Codesign (HSCD) is an integral part of modern Electronic System Level (ESL) design flows. This chapter will review important aspects of hardware/software codesign flows, summarize the historical evolution of codesign techniques, and subsequently summarize each of its major branches of research and achievements that later will be presented in detail by different parts of this Handbook of Hardware/Software Codesign.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 699.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 949.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Abbreviations

ASIC:

Application-Specific Integrated Circuit

DES:

Discrete Event Simulation

DSE:

Design Space Exploration

EA:

Evolutionary Algorithm

EDA:

Electronic Design Automation

ESL:

Electronic System Level

ForSyDe:

Formal System Design

FSM:

Finite-State Machine

GA:

Genetic Algorithm

HSCD:

Hardware/Software Codesign

HW:

Hardware

ILP:

Integer Linear Program

IP:

Intellectual Property

ISA:

Instruction-Set Architecture

KPN:

Kahn Process Network

MARTE:

Modeling and Analysis of Real-Time Embedded Systems

MoC:

Model of Computation

MPSoC:

Multi-Processor System-on-Chip

OOO PDES:

Out-of-Order Parallel Discrete Event Simulation

OS:

Operating System

PB:

Pseudo-Boolean

PDES:

Parallel Discrete Event Simulation

PN:

Process Network

SDF:

Synchronous Data Flow

SIMD:

Single Instruction, Multiple Data

SLDL:

System-Level Description Language

SoC:

System-on-Chip

SW:

Software

SysteMoC:

SystemC Models of Computation

TLM:

Transaction-Level Model

UML:

Unified Modeling Language

VLIW:

Very Long Instruction Word

VP:

Virtual Prototype

WCET:

Worst-Case Execution Time

References

  1. Aho AV, Lam MS, Sethi R, Ullman JD (2006) Compilers: principles, techniques, and tools, 2nd edn. Addison-Wesley Longman Publishing Co., Inc., Boston

    MATH  Google Scholar 

  2. Alur R, Dill DL (1994) A theory of timed automata. Theor Comput Sci 126(2):183–235

    Article  MathSciNet  MATH  Google Scholar 

  3. Antoniazzi S, Balboni A, Fornaciari W, Sciuto D (1994) A methodology for control-dominated systems codesign. In: Proceedings of the international workshop on hardware/software codesign, pp 2–9

    Google Scholar 

  4. Balarin F, Chiodo M, Giusto P, Hsieh H, Jurecska A, Lavagno L, Passerone C, Sangiovanni-Vincentelli A, Sentovich E, Suzuki K, Tabbara B (1997) Hardware-Software co-design of embedded systems: the POLIS approach. Kluwer Academic Publishers, Boston

    Book  MATH  Google Scholar 

  5. Banakar R, Steinke S, Lee BS, Balakrishnan M, Marwedel P (2002) Scratchpad memory: a design alternative for cache on-chip memory in embedded systems. In: Proceedings of CODES

    Book  Google Scholar 

  6. Bengtsson J, Larsen K, Larsson F, Pettersson P, Yi W (1996) UPPAAL—a tool suite for automatic verification of real-time systems. Springer, Berlin, pp 232–243. doi:10.1007/BFb0020949

    Google Scholar 

  7. Benveniste A, Caspi P, Edwards S, Halbwachs N, Le Guernic P, de Simone R (2003) The synchronous languages twelve years later. Proc IEEE 91(1):64–83

    Article  Google Scholar 

  8. Buttazzo GC (2011) Hard real-time computing systems: predictable scheduling algorithms and applications, vol 24. Springer, New York

    MATH  Google Scholar 

  9. Cassandras C, Lafortune S (2008) Introduction to discrete event systems, 2nd edn. Springer, New York

    Book  MATH  Google Scholar 

  10. Chattopadhyay S, Roychoudhury A, Rosén J, Eles P, Peng Z (2014) Time-predictable embedded software on multi-core platforms: analysis and optimization. Found TrendsⓇElectron Des Autom 8(3–4):199–356. doi:10.1561/1000000037

    Article  Google Scholar 

  11. Clarke EM, Emerson EA, Sistla AP (1986) Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Trans Program Lang Syst 8(2):244–263

    Article  MATH  Google Scholar 

  12. Clarke EM, Grumberg O, Peled DA (1999) Model checking. MIT Press, Cambridge

    Google Scholar 

  13. Coussy P, Morawiec A (2008) High-level synthesis: from algorithm to digital circuit, 1st edn. Springer, Dordrecht

    Book  Google Scholar 

  14. Densmore D, Passerone R, Sangiovanni-Vincentelli A (2006) A platform-based taxonomy for ESL design. IEEE Des Test Comput 23:359–374

    Article  Google Scholar 

  15. Edwards S, Lavagno L, Lee EA, Sangiovanni-Vincentelli A (1997) Design of embedded systems: formal models, validation, and synthesis. Proc IEEE 85(3):366–390

    Article  Google Scholar 

  16. Eichenberger AE, O’Brien JK, O’Brien KM, Wu P, Chen T, Oden PH, Prener DA, Shepherd JC, So B, Sura Z, Wang A, Zhang T, Zhao P, Gschwind MK, Archambault R, Gao Y, Koo R (2006) Using advanced compiler technology to exploit the performance of the cell broadband engineTM architecture. IBM Syst J 45:59–84

    Article  Google Scholar 

  17. Gajski DD, Dutt N, Wu A, Lin S (1992) High level synthesis: introduction to chip and system design. Springer, New York

    Book  Google Scholar 

  18. Gerstlauer A, Haubelt C, Pimentel A, Stefanov T, Gajski D, Teich J (2009) Electronic system-level synthesis methodologies. IEEE Trans Comput Aided Des Integr Circuits Syst 28(10):1517–1530

    Article  Google Scholar 

  19. Girault A, Lee B, Lee EA (1999) Hierarchical finite state machines with multiple concurrency models. IEEE Trans Comput Aided Des Integr Circuits Syst 18(6):742–760

    Article  Google Scholar 

  20. Harel D (1987) Statecharts: a visual formalism for complex systems. Sci Comput Program 8(3):231–274

    Article  MathSciNet  MATH  Google Scholar 

  21. Hoare C (1985) Communicating sequential processes. Prentice Hall, Englewood Cliffs

    MATH  Google Scholar 

  22. Kahn G (1974) The semantics of a simple language for parallel programming. In: Proceedings of IFIP congress 74. North-Holland Publishing Co

    Google Scholar 

  23. Kalavade A, Lee, EA (1993) A hardware/software codesign methodology for DSP applications. IEEE Des Test Comput 10(3):16–28

    Article  Google Scholar 

  24. Lattner C, Adve V (2004) LLVM: a compilation framework for lifelong program analysis & transformation. In: Proceedings of the 2004 international symposium on code generation and optimization (CGO’04), Palo Alto

    Google Scholar 

  25. Lee EA, Parks TM (1995) Dataflow process networks. Proc IEEE 83:773–799

    Article  Google Scholar 

  26. Lee EA, Sangiovanni-Vincentelli A (1998) A framework for comparing models of computation. IEEE Trans Comput Aided Des Integr Circuits Syst 17(12):1217–1229

    Article  Google Scholar 

  27. Prakash S, Parker AC (1992) SOS: synthesis of application-specific heterogeneous multiprocessor systems. J Parallel Distrib Comput 16(4):338–351

    Article  MATH  Google Scholar 

  28. Redd B, Kellis S, Gaskin N, Brown R (2014) The impact of process scaling on scratchpad memory energy savings. J Low Power Electron Appl 4(3):231. http://www.mdpi.com/2079-9268/4/3/231

  29. Saleh R, Wilton S, Mirabbasi S, Hu A, Greenstreet M, Lemieux G, Pande PP, Grecu C, Ivanov A (2006) System-on-chip: reuse and integration. Proc IEEE 94(6):1050–1069. doi:10.1109/JPROC.2006.873611

    Article  Google Scholar 

  30. Stallman RM, DeveloperCommunity G (2009) Using the GNU compiler collection: a GNU manual for GCC version 4.3.3. CreateSpace, Paramount

    Google Scholar 

  31. Teich J (2012) Hardware/Software codesign: the past, the present, and predicting the future. Proc IEEE 100(Special Centennial Issue):1411–1430. doi:10.1109/JPROC.2011.2182009

  32. Teich J, Blickle T, Thiele L (1997) An evolutionary approach to system-level synthesis. In: Proceedings of the international workshop on hardware/software codesign (CODES/CASHE), pp 167–171

    Google Scholar 

  33. Wilhelm R, Engblom J, Ermedahl A, Holsti N, Thesing S, Whalley D, Bernat G, Ferdinand C, Heckmann R, Mitra T, Mueller F, Puaut I, Puschner P, Staschulat J, Stenstrom P (2008) The worst-case execution time problem–overview of methods and survey of tools. ACM Trans Embed Comput Syst 7(3):Art. 36

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Gwanak-ro 1, Gwanak-gu, Seoul, Korea

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

  3. Department of Computer Science and Electrical Engineering, Institute of Applied Microelectronics and Computer Engineering, University of Rostock, Rostock, Germany

    Christian Haubelt

  4. Institute of Embedded Systems/Real-Time Systems at Ulm University, Ulm, Germany

    Michael Glaß

  5. Department of Computer Science, School of Computing, National University of Singapore, Singapore, Singapore

    Tulika Mitra

  6. Center for Embedded and Cyber-Physical Systems, Department of Electrical Engineering and Computer Science, The Henry Samueli School of Engineering, University of California, Irvine, CA, USA

    Rainer Dömer

  7. Department of Computer and Information Science, Linköping University, SE-581 83, Linköping, Sweden

    Petru Eles

  8. School of Computing, Informatics and Decision Systems Engineering, Arizona State University, 85287, Tempe, AZ, USA

    Aviral Shrivastava

  9. Department of Electrical and Computer Engineering, The University of Texas at Austin, 78712, Austin, TX, USA

    Andreas Gerstlauer

  10. Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies, University of Maryland, College Park, MD, USA

    Shuvra S. Bhattacharyya

  11. Department of Pervasive Computing, Tampere University of Technology, Tampere, Finland

    Shuvra S. Bhattacharyya

Authors
  1. Soonhoi Ha
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jürgen Teich
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Christian Haubelt
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Michael Glaß
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Tulika Mitra
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Rainer Dömer
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Petru Eles
    View author publications

    You can also search for this author in PubMed Google Scholar

  8. Aviral Shrivastava
    View author publications

    You can also search for this author in PubMed Google Scholar

  9. Andreas Gerstlauer
    View author publications

    You can also search for this author in PubMed Google Scholar

  10. Shuvra S. Bhattacharyya
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Soonhoi Ha .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer Science+Business Media Dordrecht

About this entry

Cite this entry

Ha, S. et al. (2017). Introduction to Hardware/Software Codesign. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_41

Download citation

Publish with us

Policies and ethics

Search

Navigation