Skip to main content
SpringerLink
Log in

SysteMoC: A Data-Flow Programming Language for Codesign

  • Reference work entry
  • First Online:
Handbook of Hardware/Software Codesign

  • 3212 Accesses

Abstract

Computations in hardware/software systems are inherently performed concurrently. Hence, modeling hardware/software systems requires notions of concurrency. Data-flow models have been and are still successfully applied in the modeling of hardware/software systems. In this chapter, we motivate and introduce the usage of data-flow models. Moreover, we discuss the expressiveness and analyzability of different data-flow Models of Computation (MoCs). Subsequently, we present SysteMoC, an approach supporting many data-flow MoCs based on the system description language SystemC. Besides specifying data-flow models, SystemMoC also permits the automatic classification of each different part of an application modeled in SysteMoC into a least expressive but most analyzable MoC. This classification is the key to further optimization in later design stages of hardware/software systems such as exploration of design alternatives as well as automatic code generation and hardware synthesis. Such optimization and refinement steps are employed as part of the SystemCoDesigner design flow that uses SysteMoC as its input language.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 699.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 949.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Abbreviations

BDF:

Boolean Data Flow

CIC:

Common Intermediate Code

CPU:

Central Processing Unit

CSDF:

Cyclo-Static Data Flow

DDF:

Dennis Data Flow

DFG:

Data-Flow Graph

DSE:

Design Space Exploration

FIFO:

First-In First-Out

FSM:

Finite-State Machine

FunState:

Functions Driven by State Machines

HSCD:

Hardware/Software Codesign

HSDF:

Homogeneous (Synchronous) Data Flow

KPN:

Kahn Process Network

MoC:

Model of Computation

NDF:

Non-Determinate Data Flow

SDF:

Synchronous Data Flow

SysteMoC:

SystemC Models of Computation

References

  1. Bhattacharya B, Bhattacharyya SS (2001) Parameterized dataflow modeling for DSP systems. IEEE Trans Signal Process 49(10):2408–2421. doi:10.1109/78.950795

    Article  MathSciNet  MATH  Google Scholar 

  2. Bhattacharyya SS, Murthy PK, Lee EA (1997) APGAN and RPMC: complementary heuristics for translating DSP block diagrams into efficient software implementations. J Des Autom Embed Syst 2:33

    Article  Google Scholar 

  3. Bilsen G, Engels M, Lauwereins R, Peperstraete J (1996) Cyclo-static dataflow. IEEE Trans Signal Process 44(2):397–408

    Article  Google Scholar 

  4. Blickle T, Teich J, Thiele L (1998) System-level synthesis using evolutionary algorithms. Des Autom Embed Syst 3(1):23–58

    Article  Google Scholar 

  5. Buck JT (1993) Scheduling dynamic dataflow graphs with bounded memory using the token flow model. Ph.D dissertation, Department of EECS, University of California, Berkeley. Technical Report UCB/ERL 93/69

    Google Scholar 

  6. Commoner F, Holt AW, Even S, Pnueli A (1971) Marked directed graphs. J Comput Syst Sci 5(5):511–523. doi:10.1016/S0022-0000(71)80013-2

    Article  MathSciNet  MATH  Google Scholar 

  7. Dennis J (1974) First version of a data flow procedure language. In: Robinet B (ed) Programming symposium. Lecture notes in computer science, vol 19. Springer, Berlin/Heidelberg, pp 362–376. doi:10.1007/3-540-06859-7_145

    Chapter  Google Scholar 

  8. Eker J, Janneck JW, Lee EA, Liu J, Liu X, Ludvig J, Neuendorffer S, Sachs S, Xiong Y (2003) Taming heterogeneity – the ptolemy approach. Proc IEEE 91(1):127–144. doi:10.1109/JPROC.2002.805829

    Article  Google Scholar 

  9. Falk J (2015) A clustering-based MPSoC design flow for data flow-oriented applications. Dr. Hut, Sternstr. 18, München. Dissertation Friedrich-Alexander-Universität Erlangen-Nürnberg

    Google Scholar 

  10. Falk J, Haubelt C, Teich J (2005) Syntax and execution behavior of SysteMoC. Technical report. 04-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen

    Google Scholar 

  11. Falk J, Haubelt C, Teich J (2006) Efficient representation and simulation of model-based designs in systemC. In: Proceedings of the forum on specification and design languages (FDL 2006), pp 129–134

    Google Scholar 

  12. Falk J, Haubelt C, Zebelein C, Teich J (2013) Integrated modeling using finite state machines and dataflow graphs. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of signal processing systems. Springer, Berlin/Heidelberg, pp 975–1013

    Chapter  Google Scholar 

  13. Falk J, Keinert J, Haubelt C, Teich J, Bhattacharyya SS (2008) A generalized static data flow clustering algorithm for MPSoC scheduling of multimedia applications. In: Proceedings of the 8th ACM international conference on embedded software (EMSOFT 2008). ACM, New York, pp 189–198. doi:10.1145/1450058.1450084

    Google Scholar 

  14. Falk J, Schwarzer T, Glaß M, Teich J, Zebelein C, Haubelt C (2015) Quasi-static scheduling of data flow graphs in the presence of limited channel capacities. In: Proceedings of the 13th IEEE symposium on embedded systems for real-time multimedia (ESTIMEDIA 2015) p 10

    Google Scholar 

  15. Falk J, Schwarzer T, Zhang L, Glaß M, Teich J (2015) Automatic communication-driven virtual prototyping and design for networked embedded systems. Microprocess Microsyst 39(8):1012–1028. doi:10.1016/j.micpro.2015.08.008

    Article  Google Scholar 

  16. Falk J, Zebelein C, Haubelt C, Teich J (2011) A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. In: Proceedings of the design, automation and test in Europe (DATE 2011). IEEE, pp 521–526

    Google Scholar 

  17. Falk J, Zebelein C, Haubelt C, Teich J (2013) A rule-based quasi-static scheduling approach for static Islands in dynamic dataflow graphs. ACM Trans Embed Comput Syst 12(3):74:1–74:31. doi:10.1145/2442116.2442124

  18. Falk J, Zebelein C, Keinert J, Haubelt C, Teich J, Bhattacharyya, SS (2011) Analysis of systemC actor networks for efficient synthesis. ACM Trans embed Comput Syst 10(2):18:1–18:34. doi:10.1145/1880050.1880054

  19. Girault A, Lee B, Lee E (1999) Hierarchical finite state machines with multiple concurrency models. IEEE Trans Comput Aided Des Integr Circuits Syst 18(6):742–760

    Article  Google Scholar 

  20. Gouda MG (1980) Liveness of marked graphs and communication and VLSI systems represented by them. Technical report, Austin

    Google Scholar 

  21. Gu R, Janneck JW, Raulet M, Bhattacharyya SS (2011) Exploiting statically schedulable regions in dataflow programs. Signal Processing Syst 63(1):129–142. doi:10.1007/s11265-009-0445-1

    Article  Google Scholar 

  22. Hsu CJ, Bhattacharyya SS (2007) Cycle-breaking techniques for scheduling synchronous dataflow graphs. Technical report. UMIACS-TR-2007-12, Institute for Advanced Computer Studies, University of Maryland at College Park

    Google Scholar 

  23. Hylands C, Lee E, Liu J, Liu X, Neuendorffer S, Xiong Y, Zhao Y, Zheng H (2004) Overview of the ptolemy project, technical memorandum no. UCB/ERL M03/25. Technical report, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley

    Google Scholar 

  24. Kahn G (1974) The semantics of a simple language for parallel programming. In: IFIP Congress, pp 471–475

    MATH  Google Scholar 

  25. Keinert J, Streubühr M, Schlichter T, Falk J, Gladigau J, Haubelt C, Teich J, Meredith M (2009) SystemCoDesigner – an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. Trans Des Autom Electron Syst 14(1):1:1–1:23

    Google Scholar 

  26. Kosinski PR (1978) A straightforward denotational semantics for non-determinate data flow programs. In: Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on principles of programming languages (POPL 1978). ACM, New York, pp 214–221. doi:10.1145/512760.512783

    Google Scholar 

  27. Lee EA (2006) The problem with threads. Technical report. UCB/EECS-2006-1, EECS Department, University of California, Berkeley. The published version of this paper is in IEEE Computer 39(5):33–42, May 2006

    Google Scholar 

  28. Lee EA, Messerschmitt DG (1987) Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans Comput 36(1):24–35. doi:10.1109/TC.1987.5009446

    Article  Google Scholar 

  29. Lee EA, Messerschmitt DG (1987) Synchronous data flow. Proc IEEE 75(9):1235–1245

    Article  Google Scholar 

  30. Lee EA, Sangiovanni-Vincentelli AL (1998) A framework for comparing models of computation. IEEE Trans Comput Aided Des Integr Circuits Syst 17(12):1217–1229. doi:10.1109/43.736561

    Article  Google Scholar 

  31. Parks TM (1995) Bounded scheduling of process networks. Ph.D dissertation, Department of EECS, University of California, Berkeley. http://www.eecs.berkeley.edu/Pubs/TechRpts/1995/2926.html. Technical Report UCB/ERL M95/105

  32. Pino JL, Bhattacharyya SS, Lee E (1995) A hierarchical multiprocessor scheduling system for DSP applications. In: Proceedings of the Asilomar conference on signals, systems, and computers, vol 1, pp 122–126. doi:10.1109/ACSSC.1995.540525

  33. Plishker W, Sane N, Kiemb M, Anand K, Bhattacharyya SS (2008) Functional DIF for rapid prototyping. In: The 19th IEEE/IFIP international symposium on rapid system prototyping (RSP 2008), pp 17–23. doi:10.1109/RSP.2008.32

  34. Plishker W, Sane N, Kiemb M, Bhattacharyya SS (2008) Heterogeneous design in functional DIF. In: Proceedings of the 8th international workshop on embedded computer systems: architectures, modeling, and simulation (SAMOS 2008). Springer, Berlin/Heidelberg, pp 157–166. doi:10.1007/978-3-540-70550-5_18

    Chapter  Google Scholar 

  35. Ptolemaeus C (ed) (2014) System design, modeling, and simulation using Ptolemy II. Ptolemy.org, Berkeley. http://ptolemy.org/systems

  36. Rosales R, Glaß M, Teich J, Wang B, Xu Y, Hasholzner R (2014) Maestro – holistic actor-oriented modeling of nonfunctional properties and firmware behavior for mpsocs. ACM Trans Des Autom Electron Syst (TODAES) 19(3):23:1–23:26. doi:10.1145/2594481

  37. Schwarzer T, Falk J, Glaß M, Teich J, Zebelein C, Haubelt C (2015) Throughput-optimizing compilation of dataflow applications for multi-cores using quasi-static scheduling. In: Stuijk S (ed) Proceedings of the 18th international workshop on software and compilers for embedded systems (SCOPES 2015). ACM, Berlin, pp 68–75

    Chapter  Google Scholar 

  38. Streubühr M, Falk J, Haubelt C, Teich J, Dorsch R, Schlipf T (2006) Task-accurate performance modeling in systemC for real-time multi-processor architectures. In: Gielen GGE (ed) Proceedings of design, automation and test in Europe (DATE 2006). European Design and Automation Association, Leuven, pp 480–481. doi:10.1145/1131610

    Google Scholar 

  39. Streubühr M, Gladigau J, Haubelt C, Teich J (2010) Efficient approximately-timed performance modeling for architectural exploration of MPSoCs. In: Borrione D (ed) Advances in design methods from modeling languages for embedded systems and SoC’s. Lecture notes in electrical engineering, vol 63. Springer, Berlin/Heidelberg, pp 59–72. doi:10.1007/978-90-481-9304-2_4

    Chapter  Google Scholar 

  40. Stuijk S, Geilen M, Theelen BD, Basten T (2011) Scenario-aware dataflow: modeling, analysis and implementation of dynamic applications. In: Proceedings of the international conference on embedded computer systems: architectures, modeling, and simulation (ICSAMOS 2011). IEEE Computer Society, pp 404–411. doi:10.1109/SAMOS.2011.6045491

  41. Thiele L, Strehl K, Ziegenbein D, Ernst R, Teich J (1999) FunState – an internal design representation for codesign. In: White JK, Sentovich E (eds) ICCAD. IEEE, pp 558–565

    Google Scholar 

  42. Thiele L, Teich J, Naedele M, Strehl K, Ziegenbein D (1998) SCF – state machine controlled flow diagrams. Technical report, Computer Engineering and Networks Lab (TIK), Swiss Federal Institute of Technology (ETH), Zurich, Gloriastrasse 35, CH-8092. Technical Report TIK-33

    Google Scholar 

  43. Xu Y, Rosales R, Wang B, Streubühr M, Hasholzner R, Haubelt C, Teich J (2012) A very fast and quasi-accurate power-state-based system-level power modeling methodology. In: Herkersdorf A, Römer K, Brinkschulte U (eds) Proceedings of the architecture of computing systems (ARCS 2012), vol 7179. Springer, Berlin/Heidelberg, pp 37–49. doi:10.1007/978-3-642-28293-5_4

    Chapter  Google Scholar 

  44. Zebelein C (2014) A model-based approach for the specification and refinement of streaming applications. Ph.D. thesis, University of Rostock

    Google Scholar 

  45. Zebelein C, Falk J, Haubelt C, Teich J (2008) Classification of general data flow actors into known models of computation. In: Proceedings 6th ACM/IEEE international conference on formal methods and models for codesign (MEMOCODE 2008), pp 119–128

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Joachim Falk & Jürgen Teich

  2. Department of Computer Science and Electrical Engineering, Institute of Applied Microelectronics and Computer Engineering, University of Rostock, Richard-Wagner Str. 31, 18119, Rostock, Germany

    Christian Haubelt

  3. Valeo Siemens eAutomotive Germany GmbH, Frauenauracher Str. 85, 91058, Erlangen, Germany

    Christian Zebelein

Authors
  1. Joachim Falk
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Christian Haubelt
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jürgen Teich
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Christian Zebelein
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Joachim Falk .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer Science+Business Media Dordrecht

About this entry

Cite this entry

Falk, J., Haubelt, C., Teich, J., Zebelein, C. (2017). SysteMoC: A Data-Flow Programming Language for Codesign. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_4

Download citation

Publish with us

Policies and ethics

Search

Navigation