A technique for the design of systolic arrays with bit-level pipelining B. B. MadanS. R. ParkerM. Zubair OriginalPaper Pages: 139 - 151
Fault-tolerant VLSI sorters P. J. VarmanI. V. RamakrishnanD. S. Fussell OriginalPaper Pages: 153 - 174
Construction of a fault-tolerant grid of processors for wafer-scale integration Alessandro Zorat OriginalPaper Pages: 175 - 189
Applications of VLSI technology in a massively parallel machine David Elliot Shaw OriginalPaper Pages: 191 - 215
Designing VLSI network nodes to reduce memory traffic in a shared memory parallel computer Susan DickeyAllan GottliebYue -Sheng Liu OriginalPaper Pages: 217 - 238
Active memory chips: A brief survey and case study David Elliot ShawTheodore M. Sabety OriginalPaper Pages: 239 - 259