A Practical Parallel Architecture for Stacks Filters María J. AvedilloJosé M. QuintanaAntonio Jiménez-Calderón OriginalPaper 01 November 2004 Pages: 91 - 100
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization Sangjin HongShu-Shin ChinWei Hwang OriginalPaper 01 November 2004 Pages: 101 - 113
Ultra Low Power CORDIC Processor for Wireless Communication Algorithms Konstantinos SarrigeorgidisJan Rabaey OriginalPaper 01 November 2004 Pages: 115 - 130
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization Shuvra S. BhattacharyyaPraveen K. Murthy OriginalPaper 01 November 2004 Pages: 131 - 146
Iris Recognition Using Wavelet Features Jaemin KimSeongwon ChoRobert J. Marks II OriginalPaper 01 November 2004 Pages: 147 - 156
Operating Margin-Oriented Design Methods for Threshold Element-Based Reconfigurable Logic Circuits Realizing any Symmetric Function Kazuo Aoyama OriginalPaper 01 November 2004 Pages: 157 - 171
Scalable Parallel Memory Architectures for Video Coding Jarno K. TanskanenJarkko T. Niittylahti OriginalPaper 01 November 2004 Pages: 173 - 199