Guest Editor's Introduction Elias S. ManolakosWayne Burleson OriginalPaper 01 February 2000 Pages: 5 - 6
Efficient Wordlength Reduction Techniques for DSP Applications Paul D. Fiore OriginalPaper 01 February 2000 Pages: 9 - 18
A Hierarchical Block-Floating-Point Arithmetic Shiro KobayashiGerhard P. Fettweis OriginalPaper 01 February 2000 Pages: 19 - 30
DCT-Domain Embedded Memory Compression for Hybrid Video Coders Richard P. KleihorstRené J. Van Der Vleuten OriginalPaper 01 February 2000 Pages: 31 - 41
Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications Sangjin HongWayne E. Stark OriginalPaper 01 February 2000 Pages: 43 - 57
Partitioning Analog and Digital Processing in Mixed-Signal Systems Sydney ReaderWon NamgoongTeresa Meng OriginalPaper 01 February 2000 Pages: 59 - 65
Linear QR Architecture for a Single Chip Adaptive Beamformer G. LightbodyR. WalkeJ. McCanny OriginalPaper 01 February 2000 Pages: 67 - 81
Multidimensional Exploration of Software Implementations for DSP Algorithms Eckart ZitzlerJürgen TeichShuvra S. Bhattacharyya OriginalPaper 01 February 2000 Pages: 83 - 98
DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures Andrew StoneElias S. Manolakos OriginalPaper 01 February 2000 Pages: 99 - 120