Volume 51, Issue 3

Search all Journal of Signal Processing Systems articles

June 2008

Special Issue: Design and Programming of Signal Processors for Multimedia Communication. Guest Editors: Yen-Kuang Chen, David W. Lin, John V. McCanny and Edwin H.-M. Sha

7 articles in this issue

Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication
Yen-Kuang Chen
David W. Lin
Edwin H.-M. Sha
EditorialNotes 12 January 2008 Pages: 207 - 208
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications
Tay-Jyi Lin
Shin-Kai Chen
Pi-Chen Hsiao
BriefCommunication 20 August 2007 Pages: 209 - 223
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
B. Mei
B. De Sutter
S. Dupont
BriefCommunication 20 December 2007 Pages: 225 - 243
An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor
Shuenn-Shyang Wang
Chien-Sung Li
BriefCommunication 28 June 2007 Pages: 245 - 256
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch
Kun-Yuan Hsieh
Yung-Chia Lin
Jenq-Kuen Lee
BriefCommunication 28 June 2007 Pages: 257 - 268
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
Yung-Chia Lin
Chia Han Lu
Jenq-Kuen Lee
BriefCommunication 28 June 2007 Pages: 269 - 288
Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW–SIMD DSP
Wonchul Lee
Hyojin Choi
Wonyong Sung
BriefCommunication 10 January 2008 Pages: 289 - 302

Volume 51, Issue 3

Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW–SIMD DSP

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