1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 111 - 111

2. A method for automatic design error location and correction in combinational logic circuits

   • Ayman M. Wahba
   • Dominique Borrione

   OriginalPaper Pages: 113 - 127

3. An algebra of multiple faults in RAMs

   • J. A. Brzozowski
   • H. Jürgensen

   OriginalPaper Pages: 129 - 142

4. Fault simulation for mixed-signal systems

   • Pascal Caunegre
   • Claude Abraham

   OriginalPaper Pages: 143 - 152

5. A new reconfigurable Test Vector Generator for built-in self-test applications

   • Samir Boubezari
   • Bozena Kaminska

   OriginalPaper Pages: 153 - 164

6. A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST

   • Michael Goessel
   • Egor S. Sogomonyan

   OriginalPaper Pages: 165 - 177

7. Monitoring machine based synthesis technique for concurrent error detection in finite state machines

   • R. A. Parekhji
   • G. Venkatesh
   • S. D. Sherlekar

   OriginalPaper Pages: 179 - 201

8. SeparateI _DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis

   • Manoj Sachdev

   OriginalPaper Pages: 203 - 214

9. Hazard simulation of sequential circuits

   • Kanji Hirabayashi

   OriginalPaper Pages: 215 - 217

10. An efficient built-in self test method for robust path delay fault testing

    • Ioannis Voyiatzis
    • Antonis Paschalis
    • Constantin Halatsis

    OriginalPaper Pages: 219 - 222